From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 23401821DE for ; Mon, 20 Feb 2017 00:29:36 -0800 (PST) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga105.fm.intel.com with ESMTP; 20 Feb 2017 00:29:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,185,1484035200"; d="scan'208";a="227411917" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga004.fm.intel.com with ESMTP; 20 Feb 2017 00:29:35 -0800 Received: from fmsmsx113.amr.corp.intel.com (10.18.116.7) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 20 Feb 2017 00:29:35 -0800 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by FMSMSX113.amr.corp.intel.com (10.18.116.7) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 20 Feb 2017 00:29:35 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.88]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.204]) with mapi id 14.03.0248.002; Mon, 20 Feb 2017 16:29:31 +0800 From: "Fan, Jeff" To: "Fan, Jeff" , "edk2-devel@lists.01.org" Thread-Topic: [edk2] [PATCH] Fix SMRR2 bug. Thread-Index: AQHSi1L6RXXZAIYerUG89b0r57Vgu6Fxj4kg Date: Mon, 20 Feb 2017 08:29:31 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C5405D5@shsmsx102.ccr.corp.intel.com> References: <20170220082515.16796-1-jeff.fan@intel.com> In-Reply-To: <20170220082515.16796-1-jeff.fan@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZjFiOTliMDUtNTM0MS00NDZhLThkNzYtYjJhZmIxYzgyY2FiIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6ImRsUWc2UkNJZTJqeXEydXZmaW9vQWdtZzRvTEl3aDdKNDV2aDVrbWxKWFk9In0= x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] Fix SMRR2 bug. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 20 Feb 2017 08:29:36 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Please ignore this patch. This is not the final patch and sent out wrongly.= Sorry for it. Jeff -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Jeff= Fan Sent: Monday, February 20, 2017 4:25 PM To: edk2-devel@lists.01.org Subject: [edk2] [PATCH] Fix SMRR2 bug. Signed-off-by: Jeff Fan --- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 54 ++++++++++++++++++--------= ---- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 2 ++ UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 25 ++++++++++++-- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h | 5 +++ UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 14 +++----- 5 files changed, 66 insertions(+), 34 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index fc7714a..f01a896 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -939,6 +939,9 @@ PiCpuSmmEntry ( return EFI_SUCCESS; } =20 +EFI_SMRAM_DESCRIPTOR *mSmramRanges; +UINTN mSmramRangeCount; + /** =20 Find out SMRAM information including SMRR base and SMRR size. @@ -957,8 +960,6 @@ FindSmramInfo ( UINTN Size; EFI_SMM_ACCESS2_PROTOCOL *SmmAccess; EFI_SMRAM_DESCRIPTOR *CurrentSmramRange; - EFI_SMRAM_DESCRIPTOR *SmramRanges; - UINTN SmramRangeCount; UINTN Index; UINT64 MaxSize; BOOLEAN Found; @@ -976,31 +977,35 @@ FindSmramInfo ( Status =3D SmmAccess->GetCapabilities (SmmAccess, &Size, NULL); ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); =20 - SmramRanges =3D (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size); - ASSERT (SmramRanges !=3D NULL); + mSmramRanges =3D (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size); ASSERT=20 + (mSmramRanges !=3D NULL); =20 - Status =3D SmmAccess->GetCapabilities (SmmAccess, &Size, SmramRanges); + Status =3D SmmAccess->GetCapabilities (SmmAccess, &Size, mSmramRanges); ASSERT_EFI_ERROR (Status); =20 - SmramRangeCount =3D Size / sizeof (EFI_SMRAM_DESCRIPTOR); + mSmramRangeCount =3D Size / sizeof (EFI_SMRAM_DESCRIPTOR); =20 // // Find the largest SMRAM range between 1MB and 4GB that is at least 256= K - 4K in size // CurrentSmramRange =3D NULL; - for (Index =3D 0, MaxSize =3D SIZE_256KB - EFI_PAGE_SIZE; Index < SmramR= angeCount; Index++) { + for (Index =3D 0, MaxSize =3D SIZE_256KB - EFI_PAGE_SIZE; Index < mSmram= RangeCount; Index++) { + DEBUG ((DEBUG_ERROR, "%a, %d SmramRange[%d] CpuStart =3D %x PhysicalS= ize =3D %x\n", __FUNCTION__, __LINE__, + Index, mSmramRanges[Index].CpuStart, =20 + mSmramRanges[Index].PhysicalSize)); // // Skip any SMRAM region that is already allocated, needs testing, or = needs ECC initialization // - if ((SmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTI= NG | EFI_NEEDS_ECC_INITIALIZATION)) !=3D 0) { + if ((mSmramRanges[Index].RegionState & (EFI_ALLOCATED |=20 + EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) !=3D 0) { continue; } - - if (SmramRanges[Index].CpuStart >=3D BASE_1MB) { - if ((SmramRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize) = <=3D BASE_4GB) { - if (SmramRanges[Index].PhysicalSize >=3D MaxSize) { - MaxSize =3D SmramRanges[Index].PhysicalSize; - CurrentSmramRange =3D &SmramRanges[Index]; + DEBUG ((DEBUG_ERROR, "%a, %d SmramRange[%d] CpuStart =3D %x PhysicalS= ize =3D %x\n", __FUNCTION__, __LINE__, + Index, mSmramRanges[Index].CpuStart,=20 + mSmramRanges[Index].PhysicalSize)); + + if (mSmramRanges[Index].CpuStart >=3D BASE_1MB) { + if ((mSmramRanges[Index].CpuStart + mSmramRanges[Index].PhysicalSize= ) <=3D BASE_4GB) { + if (mSmramRanges[Index].PhysicalSize >=3D MaxSize) { + MaxSize =3D mSmramRanges[Index].PhysicalSize; + CurrentSmramRange =3D &mSmramRanges[Index]; } } } @@ -1013,20 +1018,25 @@ FindSmramInfo ( =20 do { Found =3D FALSE; - for (Index =3D 0; Index < SmramRangeCount; Index++) { - if (SmramRanges[Index].CpuStart < *SmrrBase && *SmrrBase =3D=3D (Smr= amRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize)) { - *SmrrBase =3D (UINT32)SmramRanges[Index].CpuStart; - *SmrrSize =3D (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize= ); + for (Index =3D 0; Index < mSmramRangeCount; Index++) { + if (mSmramRanges[Index].CpuStart < *SmrrBase && + *SmrrBase =3D=3D (mSmramRanges[Index].CpuStart + mSmramRanges[In= dex].PhysicalSize)) { + *SmrrBase =3D (UINT32)mSmramRanges[Index].CpuStart; + *SmrrSize =3D (UINT32)(*SmrrSize +=20 + mSmramRanges[Index].PhysicalSize); Found =3D TRUE; - } else if ((*SmrrBase + *SmrrSize) =3D=3D SmramRanges[Index].CpuStar= t && SmramRanges[Index].PhysicalSize > 0) { - *SmrrSize =3D (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize= ); + } else if ((*SmrrBase + *SmrrSize) =3D=3D mSmramRanges[Index].CpuSta= rt && mSmramRanges[Index].PhysicalSize > 0) { + *SmrrSize =3D (UINT32)(*SmrrSize +=20 + mSmramRanges[Index].PhysicalSize); Found =3D TRUE; } } } while (Found); =20 - FreePool (SmramRanges); - DEBUG ((EFI_D_INFO, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase, *Sm= rrSize)); + DEBUG ((EFI_D_ERROR, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase,=20 + *SmrrSize)); + + for (Index =3D 0; Index < mSmramRangeCount; Index++) { + DEBUG ((EFI_D_ERROR, "mSmramRanges[%d].PhysicalStart =3D %x\n", Index,= mSmramRanges[Index].PhysicalStart)); + DEBUG ((EFI_D_ERROR, "mSmramRanges[%d].CpuStart =3D %x\n", Index,= mSmramRanges[Index].CpuStart)); + } } =20 /** diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index 69c54fb..c29d15d 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -414,6 +414,8 @@ extern UINTN mSemaphoreSi= ze; extern SPIN_LOCK *mPFLock; extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock; extern SPIN_LOCK *mMemoryMappedLock; +extern EFI_SMRAM_DESCRIPTOR *mSmramRanges; +extern UINTN mSmramRangeCount; =20 /** Create 4G PageTable in SMRAM. diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDx= eSmm/SmmProfile.c index f53819e..761e9a3 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -244,6 +244,23 @@ DebugExceptionHandler ( ClearTrapFlag (SystemContext); } =20 +BOOLEAN +IsInSmmRange ( + IN EFI_PHYSICAL_ADDRESS Address + ) +{ + UINTN Index; + + for (Index =3D 0; Index < mSmramRangeCount; Index++) { + if (Address >=3D mSmramRanges[Index].CpuStart && + Address < mSmramRanges[Index].CpuStart + mSmramRanges[Index].Physi= calSize) { + DEBUG ((EFI_D_ERROR, " JEFF: Address =3D %x\n", Address)); + return TRUE; + } + } + return FALSE; +} + /** Check if the memory address will be mapped by 4KB-page. =20 @@ -274,9 +291,11 @@ IsAddressValid ( return FALSE; =20 } else { - if ((Address < mCpuHotPlugData.SmrrBase) || - (Address >=3D mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)= ) { - *Nx =3D TRUE; +// if ((Address < mCpuHotPlugData.SmrrBase) || +// (Address >=3D mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSiz= e)) { + *Nx =3D TRUE; + if (IsInSmmRange (Address)) { + *Nx =3D FALSE; } return TRUE; } diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h b/UefiCpuPkg/PiSmmCpuDx= eSmm/SmmProfile.h index 04a3dfb..2c5ac3f 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h @@ -114,6 +114,11 @@ GetCpuIndex ( VOID ); =20 +BOOLEAN +IsInSmmRange ( + IN EFI_PHYSICAL_ADDRESS Address + ); + // // The flag indicates if execute-disable is supported by processor. // diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuD= xeSmm/X64/PageTbl.c index 17b2f4c..e86e4cf 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -822,8 +822,7 @@ SmiPFHandler ( // If a page fault occurs in SMRAM range, it might be in a SMM stack gua= rd page, // or SMM page protection violation. // - if ((PFAddress >=3D mCpuHotPlugData.SmrrBase) && - (PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)))= { + if (IsInSmmRange (PFAddress)) { CpuIndex =3D GetCpuIndex (); GuardPageAddress =3D (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex * = mSmmStackSize); if ((FeaturePcdGet (PcdCpuSmmStackGuard)) && @@ -853,13 +852,10 @@ Smi= PFHandler ( } } CpuDeadLoop (); - } - - // - // If a page fault occurs in SMM range - // - if ((PFAddress < mCpuHotPlugData.SmrrBase) || - (PFAddress >=3D mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)= ) { + } else { + // + // If a page fault does not occur in SMM range + // if ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != =3D 0) { DEBUG ((DEBUG_ERROR, "Code executed on IP(0x%lx) out of SMM range af= ter SMM is locked!\n", PFAddress)); DEBUG_CODE ( -- 2.9.3.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel