From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DA05081F40 for ; Sun, 26 Feb 2017 23:06:39 -0800 (PST) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP; 26 Feb 2017 23:06:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,213,1484035200"; d="scan'208";a="69929736" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga005.fm.intel.com with ESMTP; 26 Feb 2017 23:06:39 -0800 Received: from fmsmsx118.amr.corp.intel.com (10.18.116.18) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sun, 26 Feb 2017 23:06:39 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx118.amr.corp.intel.com (10.18.116.18) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sun, 26 Feb 2017 23:06:38 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.88]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.132]) with mapi id 14.03.0248.002; Mon, 27 Feb 2017 15:06:36 +0800 From: "Fan, Jeff" To: "Wu, Hao A" , "edk2-devel@lists.01.org" Thread-Topic: [PATCH v3 04/12] IntelFrameworkModulePkg: Refine casting expression result to bigger size Thread-Index: AQHSjyXYJKR6KRjXKUu796K+h758s6F8caKQ Date: Mon, 27 Feb 2017 07:06:36 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C549EAA@shsmsx102.ccr.corp.intel.com> References: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> <1487999555-9764-5-git-send-email-hao.a.wu@intel.com> In-Reply-To: <1487999555-9764-5-git-send-email-hao.a.wu@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZTI5YTliODAtZjdiMy00YzFiLTgxNWEtZTI0MWFkMmIxZDkxIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6InN3MndnU0JxTUEyaGRYbGVQbFlyTDlsNmNCWG9qdmRGSkhyQk9cL1IzZGRvPSJ9 x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v3 04/12] IntelFrameworkModulePkg: Refine casting expression result to bigger size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Feb 2017 07:06:40 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jeff Fan -----Original Message----- From: Wu, Hao A=20 Sent: Saturday, February 25, 2017 1:12 PM To: edk2-devel@lists.01.org Cc: Wu, Hao A; Fan, Jeff Subject: [PATCH v3 04/12] IntelFrameworkModulePkg: Refine casting expressio= n result to bigger size There are cases that the operands of an expression are all with rank less t= han UINT64/INT64 and the result of the expression is explicitly cast to UINT64/INT64 to fit the target size. An example will be: UINT32 a,b; // a and b can be any unsigned int type with rank less than UINT64, like //= UINT8, UINT16, etc. UINT64 c; c =3D (UINT64) (a + b); Some static code checkers may warn that the expression result might overflo= w within the rank of "int" (integer promotions) and the result is then cast= to a bigger size. The commit refines codes by the following rules: 1). When the expression is possible to overflow the range of unsigned int/ int: c =3D (UINT64)a + b; 2). When the expression will not overflow within the rank of "int", remove = the explicit type casts: c =3D a + b; 3). When the expression will be cast to pointer of possible greater size: UINT32 a,b; VOID *c; c =3D (VOID *)(UINTN)(a + b); --> c =3D (VOID *)((UINTN)a + b); 4). When one side of a comparison expression contains only operands with ra= nk less than UINT32: UINT8 a; UINT16 b; UINTN c; if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...} For rule 4), if we remove the 'UINTN' type cast like: if (a + b > c) {...} The VS compiler will complain with warning C4018 (signed/unsigned mismatch,= level 3 warning) due to promoting 'a + b' to type 'int'. Cc: Jeff Fan Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu --- IntelFrameworkModulePkg/Csm/BiosThunk/KeyboardDxe/BiosKeyboard.c | 4 ++-- IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/BiosSnp16.c | 4 ++-- IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/Misc.c | 14 ++++= +++------- IntelFrameworkModulePkg/Csm/BiosThunk/VideoDxe/BiosVideo.c | 4 ++-- IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBios.c | 6 +++-= -- IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBootSupport.c | 4 ++-- IntelFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c | 2 +- IntelFrameworkModulePkg/Library/GenericBdsLib/BdsMisc.c | 4 ++-- IntelFrameworkModulePkg/Library/LegacyBootManagerLib/LegacyBm.c | 2 +- IntelFrameworkModulePkg/Universal/BdsDxe/FrontPage.c | 4 ++-- IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIo.c | 4 ++-- 11 files changed, 26 insertions(+), 26 deletions(-) diff --git a/IntelFrameworkModulePkg/Csm/BiosThunk/KeyboardDxe/BiosKeyboard= .c b/IntelFrameworkModulePkg/Csm/BiosThunk/KeyboardDxe/BiosKeyboard.c index a597d99..742d009 100644 --- a/IntelFrameworkModulePkg/Csm/BiosThunk/KeyboardDxe/BiosKeyboard.c +++ b/IntelFrameworkModulePkg/Csm/BiosThunk/KeyboardDxe/BiosKeyboard.c @@ -1,7 +1,7 @@ /** @file ConsoleOut Routines that speak VGA. =20 -Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made availab= le under the terms and conditions @@ -418,7 +418,7 @@ BiosKeyboardDriverBin= dingStart ( // Check bit 6 of Feature Byte 2. // If it is set, then Int 16 Func 09 is supported // - if (*(UINT8 *)(UINTN) ((Regs.X.ES << 4) + Regs.X.BX + 0x06) & 0x40) { + if (*(UINT8 *) (((UINTN) Regs.X.ES << 4) + Regs.X.BX + 0x06) &=20 + 0x40) { // // Get Keyboard Functionality // diff --git a/IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/BiosSnp16.c b/I= ntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/BiosSnp16.c index a2a7797..b586a91 100644 --- a/IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/BiosSnp16.c +++ b/IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/BiosSnp16.c @@ -1,6 +1,6 @@ /** @file =20 -Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved.
+Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made availab= le under the terms and conditions @@ -1858,7 +1858,7 @@ Undi16SimpleNetwork= Isr ( =20 CopyMem ( Frame, - (VOID *)(UINTN) ((SimpleNetworkDevice->Isr.FrameSegSel << 4) + Sim= pleNetworkDevice->Isr.FrameOffset), + (VOID *) (((UINTN) SimpleNetworkDevice->Isr.FrameSegSel << 4) +=20 + SimpleNetworkDevice->Isr.FrameOffset), SimpleNetworkDevice->Isr.BufferLength ); Frame =3D Frame + SimpleNetworkDevice->Isr.BufferLength; diff --git a/IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/Misc.c b/IntelF= rameworkModulePkg/Csm/BiosThunk/Snp16Dxe/Misc.c index 4750b2f..a1dc867 100644 --- a/IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/Misc.c +++ b/IntelFrameworkModulePkg/Csm/BiosThunk/Snp16Dxe/Misc.c @@ -1,7 +1,7 @@ /** @file Helper Routines that use a PXE-enabled NIC option ROM. =20 -Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved.
+Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made availab= le under the terms and conditions @@ -49,7 +49,7 @@ CacheVectorAddress ( { UINT32 *Address; =20 - Address =3D (UINT32 *)(UINTN) (IVT_BASE + Vecto= rNumber * 4); + Address =3D (UINT32 *) ((UINTN) IVT_BASE + Vect= orNumber * 4); CachedVectorAddress[VectorNumber] =3D *Address; return EFI_SUCCESS; } @@ -68,7 +68,7 @@ RestoreCachedVectorAddress ( { UINT32 *Address; =20 - Address =3D (UINT32 *)(UINTN) (IVT_BASE + VectorNumber * 4); + Address =3D (UINT32 *) ((UINTN) IVT_BASE + VectorNumber * 4); *Address =3D CachedVectorAddress[VectorNumber]; return EFI_SUCCESS; } @@ -469,7 +469,7 @@ LaunchBaseCode ( =20 RomIdTableAddress =3D (UNDI_ROMID_T *) (RomAddress + OPTION_ROM_PTR->Pxe= RomIdOffset); =20 - if ((UINTN) (OPTION_ROM_PTR->PxeRomIdOffset + RomIdTableAddress->StructL= ength) > RomLength) { + if (((UINT32)OPTION_ROM_PTR->PxeRomIdOffset +=20 + RomIdTableAddress->StructLength) > RomLength) { DEBUG ((DEBUG_ERROR, "ROM ID Offset Error\n\r")); return EFI_NOT_FOUND; } @@ -754,10 +754,10 @@ LaunchBaseCode ( Print_Undi_Loader_Table (UndiLoaderTable); =20 DEBUG ((DEBUG_NET, "Display the PXENV+ and !PXE tables exported by NIC\n= \r")); - Print_PXENV_Table ((VOID *)(UINTN)((UndiLoaderTable->PXENVptr.Segment <<= 4) | UndiLoaderTable->PXENVptr.Offset)); - Print_PXE_Table ((VOID *)(UINTN)((UndiLoaderTable->PXEptr.Segment << 4) = + UndiLoaderTable->PXEptr.Offset)); + Print_PXENV_Table ((VOID *)(((UINTN)UndiLoaderTable->PXENVptr.Segment=20 + << 4) | UndiLoaderTable->PXENVptr.Offset)); + Print_PXE_Table ((VOID *)(((UINTN)UndiLoaderTable->PXEptr.Segment <<=20 + 4) + UndiLoaderTable->PXEptr.Offset)); =20 - Pxe =3D (PXE_T *)(UINTN)((UndiLoaderTable->PXEptr.Segment << 4) + UndiLo= aderTable->PXEptr.Offset); + Pxe =3D (PXE_T *)(((UINTN)UndiLoaderTable->PXEptr.Segment << 4) +=20 + UndiLoaderTable->PXEptr.Offset); SimpleNetworkDevice->Nii.Id =3D (UINT64)(UINTN) Pxe; =20 gBS->FreePool (Buffer); diff --git a/IntelFrameworkModulePkg/Csm/BiosThunk/VideoDxe/BiosVideo.c b/I= ntelFrameworkModulePkg/Csm/BiosThunk/VideoDxe/BiosVideo.c index f1c8b29..08672cf 100644 --- a/IntelFrameworkModulePkg/Csm/BiosThunk/VideoDxe/BiosVideo.c +++ b/IntelFrameworkModulePkg/Csm/BiosThunk/VideoDxe/BiosVideo.c @@ -1,7 +1,7 @@ /** @file ConsoleOut Routines that speak VGA. =20 -Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
+Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made availab= le under the terms and conditions @@ -1714,7 +1714,7 @@ BiosVideoCheckForVb= e ( // // Make sure the FrameBufferSize does not exceed the max available fra= me buffer size reported by VEB. // - ASSERT (CurrentModeData->FrameBufferSize <=3D (UINTN)(BiosVideoPrivate= ->VbeInformationBlock->TotalMemory * 64 * 1024)); + ASSERT (CurrentModeData->FrameBufferSize <=3D=20 + ((UINT32)BiosVideoPrivate->VbeInformationBlock->TotalMemory * 64 *=20 + 1024)); =20 BiosVideoPrivate->ModeData =3D ModeBuffer; } diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBios.c b/Intel= FrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBios.c index dd2e2b9..3ead2d9 100644 --- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBios.c +++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBios.c @@ -1,6 +1,6 @@ /** @file =20 -Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made availab= le under the terms and conditions @@ -144,7 +144,7 @@ LegacyBiosGetLegacyRe= gion ( ); =20 if (Regs.X.AX =3D=3D 0) { - *LegacyMemoryAddress =3D (VOID *) (UINTN) ((Regs.X.DS << 4) + Regs.X.= BX); + *LegacyMemoryAddress =3D (VOID *) (((UINTN) Regs.X.DS << 4) +=20 + Regs.X.BX); Status =3D EFI_SUCCESS; } else { Status =3D EFI_OUT_OF_RESOURCES; @@ -728,7 +728,7 @@ InstallSmbiosEventCallback ( } =20 if ((mStructureTableAddress !=3D 0) &&=20 - (mStructureTablePages < (UINTN) EFI_SIZE_TO_PAGES (EntryPointStructu= re->TableLength))) { + (mStructureTablePages < EFI_SIZE_TO_PAGES=20 + ((UINT32)EntryPointStructure->TableLength))) { // // If original buffer is not enough for the new SMBIOS table, free ori= ginal buffer and re-allocate // diff --git a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBootSupport.c = b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBootSupport.c index 52bcae2..1e098b3 100644 --- a/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBootSupport.c +++ b/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/LegacyBootSupport.c @@ -1,6 +1,6 @@ /** @file =20 -Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made availab= le under the terms and conditions @@ -91,7 +91,7 @@ PrintBbsTable ( // // Print DescString // - String =3D (CHAR8 *)(UINTN)((BbsTable[Index].DescStringSegment << 4) += BbsTable[Index].DescStringOffset); + String =3D (CHAR8 *)(((UINTN)BbsTable[Index].DescStringSegment << 4)=20 + + BbsTable[Index].DescStringOffset); if (String !=3D NULL) { DEBUG ((EFI_D_INFO," (")); for (SubIndex =3D 0; String[SubIndex] !=3D 0; SubIndex++) { diff --g= it a/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c b/IntelFramewo= rkModulePkg/Library/GenericBdsLib/BdsBoot.c index 628424d..d1da635 100644 --- a/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c +++ b/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsBoot.c @@ -227,7 +227,7 @@ BdsBuildLegacyDevNameString ( // // If current BBS entry has its description then use it. // - StringDesc =3D (UINT8 *) (UINTN) ((CurBBSEntry->DescStringSegment << 4) = + CurBBSEntry->DescStringOffset); + StringDesc =3D (UINT8 *) (((UINTN) CurBBSEntry->DescStringSegment << 4)= =20 + + CurBBSEntry->DescStringOffset); if (NULL !=3D StringDesc) { // // Only get fisrt 32 characters, this is suggested by BBS spec diff --= git a/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsMisc.c b/IntelFramew= orkModulePkg/Library/GenericBdsLib/BdsMisc.c index 2ba511a..48938b0 100644 --- a/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsMisc.c +++ b/IntelFrameworkModulePkg/Library/GenericBdsLib/BdsMisc.c @@ -569,11 +569,11 @@ CharToUint ( ) { if ((Char >=3D L'0') && (Char <=3D L'9')) { - return (UINTN) (Char - L'0'); + return (Char - L'0'); } =20 if ((Char >=3D L'A') && (Char <=3D L'F')) { - return (UINTN) (Char - L'A' + 0xA); + return (Char - L'A' + 0xA); } =20 ASSERT (FALSE); diff --git a/IntelFrameworkModulePkg/Library/LegacyBootManagerLib/LegacyBm.= c b/IntelFrameworkModulePkg/Library/LegacyBootManagerLib/LegacyBm.c index 080a436..76902ec 100644 --- a/IntelFrameworkModulePkg/Library/LegacyBootManagerLib/LegacyBm.c +++ b/IntelFrameworkModulePkg/Library/LegacyBootManagerLib/LegacyBm.c @@ -176,7 +176,7 @@ LegacyBmBuildLegacyDevNameString ( // // If current BBS entry has its description then use it. // - StringDesc =3D (CHAR8 *) (UINTN) ((CurBBSEntry->DescStringSegment << 4) = + CurBBSEntry->DescStringOffset); + StringDesc =3D (CHAR8 *) (((UINTN) CurBBSEntry->DescStringSegment << 4)= =20 + + CurBBSEntry->DescStringOffset); if (NULL !=3D StringDesc) { // // Only get fisrt 32 characters, this is suggested by BBS spec diff --= git a/IntelFrameworkModulePkg/Universal/BdsDxe/FrontPage.c b/IntelFramework= ModulePkg/Universal/BdsDxe/FrontPage.c index c771974..3bae0be 100644 --- a/IntelFrameworkModulePkg/Universal/BdsDxe/FrontPage.c +++ b/IntelFrameworkModulePkg/Universal/BdsDxe/FrontPage.c @@ -1,7 +1,7 @@ /** @file FrontPage routines to handle the callbacks and browser calls =20 -Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2004 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made availab= le under the terms and conditions of the BSD License which accompanies thi= s distribution. The full text of the license may be found at @@ -620,7 +62= 0,7 @@ ConvertProcessorToString ( =20 if (Base10Exponent >=3D 6) { FreqMhz =3D ProcessorFrequency; - for (Index =3D 0; Index < (UINTN) (Base10Exponent - 6); Index++) { + for (Index =3D 0; Index < ((UINT32)Base10Exponent - 6); Index++) { FreqMhz *=3D 10; } } else { diff --git a/IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIo.c b/IntelFram= eworkModulePkg/Universal/CpuIoDxe/CpuIo.c index 9db9dbe..9474606 100644 --- a/IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIo.c +++ b/IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIo.c @@ -1,7 +1,7 @@ /** @file Uses the services of the I/O Library to produce the CPU I/O Protocol =20 -Copyright (c) 2004 - 2012, Intel Corporation. All rights reserved.
+Copyright (c) 2004 - 2017, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials =20 @@ -141,7 +141,7 @@ CpuIoCheckParameter ( // // Check to see if Address is aligned // - if ((Address & (UINT64)(mInStride[Width] - 1)) !=3D 0) { + if ((Address & ((UINT64)mInStride[Width] - 1)) !=3D 0) { return EFI_UNSUPPORTED; } =20 -- 1.9.5.msysgit.0