From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B23B581EFA for ; Sun, 26 Feb 2017 23:28:01 -0800 (PST) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Feb 2017 23:28:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,213,1484035200"; d="scan'208";a="69405594" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga005.jf.intel.com with ESMTP; 26 Feb 2017 23:28:01 -0800 Received: from fmsmsx102.amr.corp.intel.com (10.18.124.200) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sun, 26 Feb 2017 23:28:00 -0800 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by FMSMSX102.amr.corp.intel.com (10.18.124.200) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sun, 26 Feb 2017 23:28:00 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.88]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.204]) with mapi id 14.03.0248.002; Mon, 27 Feb 2017 15:27:57 +0800 From: "Fan, Jeff" To: "Wu, Hao A" , "edk2-devel@lists.01.org" Thread-Topic: [PATCH v3 12/12] UefiCpuPkg: Refine casting expression result to bigger size Thread-Index: AQHSjyXcZY+Q26tRN0+EL8g7EmMupqF8d7cQ Date: Mon, 27 Feb 2017 07:27:56 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C54A093@shsmsx102.ccr.corp.intel.com> References: <1487999555-9764-1-git-send-email-hao.a.wu@intel.com> <1487999555-9764-13-git-send-email-hao.a.wu@intel.com> In-Reply-To: <1487999555-9764-13-git-send-email-hao.a.wu@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMzhmNzE0MGMtYThmNS00YjE5LThmMzgtNDAyNTA3Y2M0Nzg1IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6Ijd1NUw4b25DYWYxcUlJQlN1XC8rR2NXbFpHOEkzUGVmblpqMWx5U3NnRTVFPSJ9 x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v3 12/12] UefiCpuPkg: Refine casting expression result to bigger size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Feb 2017 07:28:01 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jeff Fan -----Original Message----- From: Wu, Hao A=20 Sent: Saturday, February 25, 2017 1:13 PM To: edk2-devel@lists.01.org Cc: Wu, Hao A; Fan, Jeff Subject: [PATCH v3 12/12] UefiCpuPkg: Refine casting expression result to b= igger size There are cases that the operands of an expression are all with rank less t= han UINT64/INT64 and the result of the expression is explicitly cast to UINT64/INT64 to fit the target size. An example will be: UINT32 a,b; // a and b can be any unsigned int type with rank less than UINT64, like //= UINT8, UINT16, etc. UINT64 c; c =3D (UINT64) (a + b); Some static code checkers may warn that the expression result might overflo= w within the rank of "int" (integer promotions) and the result is then cast= to a bigger size. The commit refines codes by the following rules: 1). When the expression is possible to overflow the range of unsigned int/ int: c =3D (UINT64)a + b; 2). When the expression will not overflow within the rank of "int", remove = the explicit type casts: c =3D a + b; 3). When the expression will be cast to pointer of possible greater size: UINT32 a,b; VOID *c; c =3D (VOID *)(UINTN)(a + b); --> c =3D (VOID *)((UINTN)a + b); 4). When one side of a comparison expression contains only operands with ra= nk less than UINT32: UINT8 a; UINT16 b; UINTN c; if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...} For rule 4), if we remove the 'UINTN' type cast like: if (a + b > c) {...} The VS compiler will complain with warning C4018 (signed/unsigned mismatch,= level 3 warning) due to promoting 'a + b' to type 'int'. Cc: Jeff Fan Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu --- UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c | 4 ++-- UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.c | 4 ++-- UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 8 ++++---- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 4 ++-- UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 6 +++--- 5 files changed, 13 insertions(+), 13 deletions(-) diff --git a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c b/UefiCpuPkg/CpuIo2Dxe/CpuIo2= Dxe.c index 60f4bbc..d19349d 100644 --- a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c +++ b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c @@ -1,7 +1,7 @@ /** @file Produces the CPU I/O 2 Protocol. =20 -Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 This program and the accompanying materials =20 @@ -141,7 +141,7 @@ CpuIoCheckParameter ( // // Check to see if Address is aligned // - if ((Address & (UINT64)(mInStride[Width] - 1)) !=3D 0) { + if ((Address & ((UINT64)mInStride[Width] - 1)) !=3D 0) { return EFI_UNSUPPORTED; } =20 diff --git a/UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.c b/UefiCpuPkg/CpuIo2Smm/CpuIo2= Smm.c index 7b1ad37..20b8350 100644 --- a/UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.c +++ b/UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.c @@ -1,7 +1,7 @@ /** @file Produces the SMM CPU I/O Protocol. =20 -Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials =20 are licensed and made available under the terms and conditions of the BSD = License =20 which accompanies this distribution. The full text of the license may be = found at =20 @@ -126,7 +126,7 @@ CpuIoCheckParameter ( // // Check to see if Address is aligned // - if ((Address & (UINT64)(mStride[Width] - 1)) !=3D 0) { + if ((Address & ((UINT64)mStride[Width] - 1)) !=3D 0) { return EFI_UNSUPPORTED; } =20 diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c b/UefiCpuPkg/Lib= rary/SmmCpuFeaturesLib/SmmStm.c index bb123ba..03937dc 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c @@ -1,7 +1,7 @@ /** @file SMM STM support functions =20 - Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2017, Intel Corporation. All rights=20 + reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -276,8 +276,8 @@ SmmCpuFeaturesInstallSmiHandler ( UINT32 RegEdx; EFI_PROCESSOR_INFORMATION ProcessorInfo; =20 - CopyMem ((VOID *)(UINTN)(SmBase + TXT_SMM_PSD_OFFSET), &gcStmPsd, sizeof= (gcStmPsd)); - Psd =3D (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID *)(UINTN)(SmBase + TXT_SMM= _PSD_OFFSET); + CopyMem ((VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET), &gcStmPsd,=20 + sizeof (gcStmPsd)); Psd =3D (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID=20 + *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET); Psd->SmmGdtPtr =3D GdtBase; Psd->SmmGdtSize =3D (UINT32)GdtSize; =20 @@ -317,7 +317,7 @@ SmmCpuFeaturesInstallSmiHandler ( // Copy template to CPU specific SMI handler location // CopyMem ( - (VOID*)(UINTN)(SmBase + SMM_HANDLER_OFFSET), + (VOID*)((UINTN)SmBase + SMM_HANDLER_OFFSET), (VOID*)gcStmSmiHandlerTemplate, gcStmSmiHandlerSize ); diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index fc7714a..2519e28 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -1,7 +1,7 @@ /** @file Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU. =20 -Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made availab= le under the terms and conditions of the BSD License which accompanies thi= s distribution. The full text of the license may be found at @@ -1268,7 +1= 268,7 @@ AllocateAlignedCodePages ( Status =3D gSmst->SmmFreePages (Memory, UnalignedPages); ASSERT_EFI_ERROR (Status); } - Memory =3D (EFI_PHYSICAL_ADDRESS) (AlignedMemory + EFI_PAGES_T= O_SIZE (Pages)); + Memory =3D AlignedMemory + EFI_PAGES_TO_SIZE (Pages); UnalignedPages =3D RealPages - Pages - UnalignedPages; if (UnalignedPages > 0) { // diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c b/UefiCpuPkg/PiSmmC= puDxeSmm/SmramSaveState.c index b4bc0ec..3188d43 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c @@ -1,7 +1,7 @@ /** @file Provides services to access SMRAM Save State Map =20 -Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made availab= le under the terms and conditions of the BSD License which accompanies thi= s distribution. The full text of the license may be found at @@ -690,7 +69= 0,7 @@ InstallSmiHandler ( // // Initialize PROCESSOR_SMM_DESCRIPTOR // - Psd =3D (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)(UINTN)(SmBase + SMM_PSD_OFF= SET); + Psd =3D (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase +=20 + SMM_PSD_OFFSET); CopyMem (Psd, &gcPsd, sizeof (gcPsd)); Psd->SmmGdtPtr =3D (UINT64)GdtBase; Psd->SmmGdtSize =3D (UINT32)GdtSize; @@ -731,7 +731,7 @@ InstallSmiHandler ( // Copy template to CPU specific SMI handler location // CopyMem ( - (VOID*)(UINTN)(SmBase + SMM_HANDLER_OFFSET), + (VOID*)((UINTN)SmBase + SMM_HANDLER_OFFSET), (VOID*)gcSmiHandlerTemplate, gcSmiHandlerSize ); -- 1.9.5.msysgit.0