From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D61FE81F5C for ; Sun, 26 Feb 2017 23:51:03 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP; 26 Feb 2017 23:51:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,213,1484035200"; d="scan'208";a="53302140" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga002.jf.intel.com with ESMTP; 26 Feb 2017 23:51:03 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sun, 26 Feb 2017 23:51:02 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.88]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.132]) with mapi id 14.03.0248.002; Mon, 27 Feb 2017 15:51:00 +0800 From: "Fan, Jeff" To: Leo Duran , "edk2-devel@ml01.01.org" CC: "Tian, Feng" , "Zeng, Star" , Laszlo Ersek , Brijesh Singh Thread-Topic: [PATCH v4 6/6] UefiCpuPkg/PiSmmCpuDxeSmm: Add support for PCD PcdPteMemoryEncryptionAddressOrMask Thread-Index: AQHSkFfZ661+2LF1+E2NYpbj9DuX5aF8e0VQ Date: Mon, 27 Feb 2017 07:51:00 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C54A176@shsmsx102.ccr.corp.intel.com> References: <1488130987-2544-1-git-send-email-leo.duran@amd.com> <1488130987-2544-7-git-send-email-leo.duran@amd.com> In-Reply-To: <1488130987-2544-7-git-send-email-leo.duran@amd.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZGRjZmMyZjMtMDdiYi00MzE1LWJlOWEtOTM3MTNkY2I4M2I2IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IlF3ODRqOTBqU0c5TlBUQjl1SnQ4UWVSbUJNMHpzYlc5WmlQZk5nSWxzZ289In0= x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v4 6/6] UefiCpuPkg/PiSmmCpuDxeSmm: Add support for PCD PcdPteMemoryEncryptionAddressOrMask X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Feb 2017 07:51:04 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Leo, I just saw your patch removed SetCacheability() also. I will drop my patch = in https://www.mail-archive.com/edk2-devel@lists.01.org/msg22944.html :-) Thanks! Jeff -----Original Message----- From: Leo Duran [mailto:leo.duran@amd.com]=20 Sent: Monday, February 27, 2017 1:43 AM To: edk2-devel@ml01.01.org Cc: Leo Duran; Fan, Jeff; Tian, Feng; Zeng, Star; Laszlo Ersek; Brijesh Sin= gh Subject: [PATCH v4 6/6] UefiCpuPkg/PiSmmCpuDxeSmm: Add support for PCD PcdP= teMemoryEncryptionAddressOrMask This PCD holds the address mask for page table entries when memory encrypti= on is enabled on AMD processors supporting the Secure Encrypted Virtualizat= ion (SEV) feature. The mask is applied when page tables entriees are created or modified. CC: Jeff Fan Cc: Feng Tian Cc: Star Zeng Cc: Laszlo Ersek Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran Reviewed-by: Star Zeng --- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 6 +- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 83 +++---------------= ---- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 14 ++++ UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 8 ++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 2 + UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 14 ++-- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 16 +++-- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 41 ++++++----- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c | 32 +++++---- 9 files changed, 91 insertions(+), 125 deletions(-) mode change 100644 = =3D> 100755 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c b/UefiCpuPkg/PiSmmCpu= DxeSmm/Ia32/PageTbl.c index c1f4b7e..119810a 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c @@ -2,6 +2,8 @@ Page table manipulation functions for IA-32 processors =20 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made availab= le under the terms and conditions of the BSD License which accompanies thi= s distribution. The full text of the license may be found at @@ -204,7 +20= 6,7 @@ SetPageTableAttributes ( PageTableSplitted =3D (PageTableSplitted || IsSplitted); =20 for (Index3 =3D 0; Index3 < 4; Index3++) { - L2PageTable =3D (UINT64 *)(UINTN)(L3PageTable[Index3] & PAGING_4K_AD= DRESS_MASK_64); + L2PageTable =3D (UINT64 *)(UINTN)(L3PageTable[Index3] &=20 + ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); if (L2PageTable =3D=3D NULL) { continue; } @@ -217,7 +219,7 @@ SetPageTableAttributes ( // 2M continue; } - L1PageTable =3D (UINT64 *)(UINTN)(L2PageTable[Index2] & PAGING_4K_= ADDRESS_MASK_64); + L1PageTable =3D (UINT64 *)(UINTN)(L2PageTable[Index2] &=20 + ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); if (L1PageTable =3D=3D NULL) { continue; } diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index c7aa48b..d99ad46 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -2,6 +2,8 @@ SMM MP service implementation =20 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made availab= le under the terms and conditions of the BSD License which accompanies thi= s distribution. The full text of the license may be found at @@ -781,7 +78= 3,8 @@ Gen4GPageTable ( // Set Page Directory Pointers // for (Index =3D 0; Index < 4; Index++) { - Pte[Index] =3D (UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1) + (Is32B= itPageTable ? IA32_PAE_PDPTE_ATTRIBUTE_BITS : PAGE_ATTRIBUTE_BITS); + Pte[Index] =3D (UINT64)((UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1)= ) | mAddressEncMask | + (Is32BitPageTable ? IA32_PAE_PDPTE_ATTRIBUTE_BITS :=20 + PAGE_ATTRIBUTE_BITS); } Pte +=3D EFI_PAGE_SIZE / sizeof (*Pte); =20 @@ -789,7 +792,7 @@ Gen4GPageTable ( // Fill in Page Directory Entries // for (Index =3D 0; Index < EFI_PAGE_SIZE * 4 / sizeof (*Pte); Index++) { - Pte[Index] =3D (Index << 21) | IA32_PG_PS | PAGE_ATTRIBUTE_BITS; + Pte[Index] =3D (Index << 21) | mAddressEncMask | IA32_PG_PS |=20 + PAGE_ATTRIBUTE_BITS; } =20 if (FeaturePcdGet (PcdCpuSmmStackGuard)) { @@ -797,8 +800,8 @@ Gen4GPage= Table ( GuardPage =3D mSmmStackArrayBase + EFI_PAGE_SIZE; Pdpte =3D (UINT64*)PageTable; for (PageIndex =3D Low2MBoundary; PageIndex <=3D High2MBoundary; PageI= ndex +=3D SIZE_2MB) { - Pte =3D (UINT64*)(UINTN)(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30= , 31)] & ~(EFI_PAGE_SIZE - 1)); - Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] =3D (UINT64)Pages | = PAGE_ATTRIBUTE_BITS; + Pte =3D (UINT64*)(UINTN)(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30= , 31)] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1)); + Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] =3D (UINT64)Pages |= =20 + mAddressEncMask | PAGE_ATTRIBUTE_BITS; // // Fill in Page Table Entries // @@ -809,13 +812,13 @@ Gen4GPageTable ( // // Mark the guard page as non-present // - Pte[Index] =3D PageAddress; + Pte[Index] =3D PageAddress | mAddressEncMask; GuardPage +=3D mSmmStackSize; if (GuardPage > mSmmStackArrayEnd) { GuardPage =3D 0; } } else { - Pte[Index] =3D PageAddress | PAGE_ATTRIBUTE_BITS; + Pte[Index] =3D PageAddress | mAddressEncMask |=20 + PAGE_ATTRIBUTE_BITS; } PageAddress+=3D EFI_PAGE_SIZE; } @@ -827,74 +830,6 @@ Gen4GPageTable ( } =20 /** - Set memory cache ability. - - @param PageTable PageTable Address - @param Address Memory Address to change cache ability - @param Cacheability Cache ability to set - -**/ -VOID -SetCacheability ( - IN UINT64 *PageTable, - IN UINTN Address, - IN UINT8 Cacheability - ) -{ - UINTN PTIndex; - VOID *NewPageTableAddress; - UINT64 *NewPageTable; - UINTN Index; - - ASSERT ((Address & EFI_PAGE_MASK) =3D=3D 0); - - if (sizeof (UINTN) =3D=3D sizeof (UINT64)) { - PTIndex =3D (UINTN)RShiftU64 (Address, 39) & 0x1ff; - ASSERT (PageTable[PTIndex] & IA32_PG_P); - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask); - } - - PTIndex =3D (UINTN)RShiftU64 (Address, 30) & 0x1ff; - ASSERT (PageTable[PTIndex] & IA32_PG_P); - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask); - - // - // A perfect implementation should check the original cacheability with = the - // one being set, and break a 2M page entry into pieces only when they - // disagreed. - // - PTIndex =3D (UINTN)RShiftU64 (Address, 21) & 0x1ff; - if ((PageTable[PTIndex] & IA32_PG_PS) !=3D 0) { - // - // Allocate a page from SMRAM - // - NewPageTableAddress =3D AllocatePageTableMemory (1); - ASSERT (NewPageTableAddress !=3D NULL); - - NewPageTable =3D (UINT64 *)NewPageTableAddress; - - for (Index =3D 0; Index < 0x200; Index++) { - NewPageTable[Index] =3D PageTable[PTIndex]; - if ((NewPageTable[Index] & IA32_PG_PAT_2M) !=3D 0) { - NewPageTable[Index] &=3D ~((UINT64)IA32_PG_PAT_2M); - NewPageTable[Index] |=3D (UINT64)IA32_PG_PAT_4K; - } - NewPageTable[Index] |=3D (UINT64)(Index << EFI_PAGE_SHIFT); - } - - PageTable[PTIndex] =3D ((UINTN)NewPageTableAddress & gPhyMask) | PAGE_= ATTRIBUTE_BITS; - } - - ASSERT (PageTable[PTIndex] & IA32_PG_P); - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask); - - PTIndex =3D (UINTN)RShiftU64 (Address, 12) & 0x1ff; - ASSERT (PageTable[PTIndex] & IA32_PG_P); - PageTable[PTIndex] &=3D ~((UINT64)((IA32_PG_PAT_4K | IA32_PG_CD | IA32_P= G_WT))); - PageTable[PTIndex] |=3D (UINT64)Cacheability; -} - -/** Schedule a procedure to run on the specified CPU. =20 @param[in] Procedure The address of the procedure t= o run diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c old mode 100644 new mode 100755 index fc7714a..d5b8900 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -2,6 +2,8 @@ Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU. =20 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made availab= le under the terms and conditions of the BSD License which accompanies thi= s distribution. The full text of the license may be found at @@ -97,6 +99,= 11 @@ BOOLEAN mSmmReadyToLock =3D FALSE; BOOLEAN mSmmCodeAccessCheckEnable =3D FALSE; =20 // +// Global copy of the PcdPteMemoryEncryptionAddressOrMask +// +UINT64 mAddressEncMask =3D 0; + +// // Spin lock used to serialize setting of SMM Code Access Check feature /= / SPIN_LOCK *mConfigSmmCodeAccessCheckLock =3D NULL; @@ -605,6 +612,13 @@ PiCpuSmmEntry ( DEBUG ((EFI_D_INFO, "PcdCpuSmmCodeAccessCheckEnable =3D %d\n", mSmmCodeA= ccessCheckEnable)); =20 // + // Save the PcdPteMemoryEncryptionAddressOrMask value into a global vari= able. + // Make sure AddressEncMask is contained to smallest supported address f= ield. + // + mAddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &=20 + PAGING_1G_ADDRESS_MASK_64; DEBUG ((EFI_D_INFO, "mAddressEncMask =3D=20 + 0x%lx\n", mAddressEncMask)); + + // // If support CPU hot plug, we need to allocate resources for possibly h= ot-added processors // if (FeaturePcdGet (PcdCpuHotPlugSupport)) { diff --git a/UefiCpuPkg/PiSm= mCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h index 69c54fb..71af2f1 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -2,6 +2,8 @@ Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU. =20 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made availab= le under the terms and conditions of the BSD License which accompanies thi= s distribution. The full text of the license may be found at @@ -184,7 +186,6 @@ extern EFI_SMM_CPU_PROTOCOL mSmmCpu; /// extern UINT8 mSmmSaveStateRegisterLma; =20 - // // SMM CPU Protocol function prototypes. // @@ -415,6 +416,11 @@ extern SPIN_LOCK *mPFLock; extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock; extern SPIN_LOCK *mMemoryMappedLock; =20 +// +// Copy of the PcdPteMemoryEncryptionAddressOrMask +// +extern UINT64 mAddressEncMask; + /** Create 4G PageTable in SMRAM. =20 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/UefiCpuPkg/PiSm= mCpuDxeSmm/PiSmmCpuDxeSmm.inf index d409edf..099792e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf @@ -5,6 +5,7 @@ # provides CPU specific services in SMM. # # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# # This program and the accompanying materials # are licensed and made ava= ilable under the terms and conditions of the BSD License @@ -157,6 +158,7 @= @ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStaticPageTable ## CONS= UMES gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable ## CONS= UMES + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ##= CONSUMES =20 [Depex] gEfiMpServiceProtocolGuid diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPk= g/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index 13323d5..a535389 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -119,7 +119,7 @@ GetPageTableEntry ( return NULL; } =20 - L3PageTable =3D (UINT64 *)(UINTN)(L4PageTable[Index4] & PAGING_4K_ADDR= ESS_MASK_64); + L3PageTable =3D (UINT64 *)(UINTN)(L4PageTable[Index4] &=20 + ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); } else { L3PageTable =3D (UINT64 *)GetPageTableBase (); } @@ -133,7 +133,7 @@ GetPageTableEntry ( return &L3PageTable[Index3]; } =20 - L2PageTable =3D (UINT64 *)(UINTN)(L3PageTable[Index3] & PAGING_4K_ADDRES= S_MASK_64); + L2PageTable =3D (UINT64 *)(UINTN)(L3PageTable[Index3] &=20 + ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); if (L2PageTable[Index2] =3D=3D 0) { *PageAttribute =3D PageNone; return NULL; @@ -145,7 +145,7 @@ GetPageTableEntry ( } =20 // 4k - L1PageTable =3D (UINT64 *)(UINTN)(L2PageTable[Index2] & PAGING_4K_ADDRES= S_MASK_64); + L1PageTable =3D (UINT64 *)(UINTN)(L2PageTable[Index2] &=20 + ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); if ((L1PageTable[Index1] =3D=3D 0) && (Address !=3D 0)) { *PageAttribute =3D PageNone; return NULL; @@ -304,9 +304,9 @@ SplitPage ( } BaseAddress =3D *PageEntry & PAGING_2M_ADDRESS_MASK_64; for (Index =3D 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { - NewPageEntry[Index] =3D BaseAddress + SIZE_4KB * Index + ((*PageEn= try) & PAGE_PROGATE_BITS); + NewPageEntry[Index] =3D (BaseAddress + SIZE_4KB * Index) |=20 + mAddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS); } - (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry + PAGE_ATTRIBUTE_BITS; + (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry | mAddressEncMask |=20 + PAGE_ATTRIBUTE_BITS; return RETURN_SUCCESS; } else { return RETURN_UNSUPPORTED; @@ -325,9 +325,9 @@ SplitPage ( } BaseAddress =3D *PageEntry & PAGING_1G_ADDRESS_MASK_64; for (Index =3D 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { - NewPageEntry[Index] =3D BaseAddress + SIZE_2MB * Index + IA32_PG_P= S + ((*PageEntry) & PAGE_PROGATE_BITS); + NewPageEntry[Index] =3D (BaseAddress + SIZE_2MB * Index) |=20 + mAddressEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS); } - (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry + PAGE_ATTRIBUTE_BITS; + (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry | mAddressEncMask |=20 + PAGE_ATTRIBUTE_BITS; return RETURN_SUCCESS; } else { return RETURN_UNSUPPORTED; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDx= eSmm/SmmProfile.c index f53819e..1b84e2c 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -2,6 +2,8 @@ Enable SMM profile. =20 Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made availab= le under the terms and conditions of the BSD License which accompanies thi= s distribution. The full text of the license may be found at @@ -513,7 +51= 5,7 @@ InitPaging ( // continue; } - Pde =3D (UINT64 *)(UINTN)(Pml4[Level1] & PHYSICAL_ADDRESS_MASK); + Pde =3D (UINT64 *)(UINTN)(Pml4[Level1] & ~mAddressEncMask &=20 + PHYSICAL_ADDRESS_MASK); } else { Pde =3D (UINT64*)(UINTN)mSmmProfileCr3; } @@ -530,7 +532,7 @@ InitPaging ( // continue; } - Pte =3D (UINT64 *)(UINTN)(*Pde & PHYSICAL_ADDRESS_MASK); + Pte =3D (UINT64 *)(UINTN)(*Pde & ~mAddressEncMask &=20 + PHYSICAL_ADDRESS_MASK); if (Pte =3D=3D 0) { continue; } @@ -557,9 +559,9 @@ InitPaging ( =20 // Split it for (Level4 =3D 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++) { - Pt[Level4] =3D Address + ((Level4 << 12) | PAGE_ATTRIBUTE_BITS= ); + Pt[Level4] =3D Address + ((Level4 << 12) | mAddressEncMask |=20 + PAGE_ATTRIBUTE_BITS); } // end for PT - *Pte =3D (UINTN)Pt | PAGE_ATTRIBUTE_BITS; + *Pte =3D (UINT64)(UINTN)Pt | mAddressEncMask |=20 + PAGE_ATTRIBUTE_BITS; } // end if IsAddressSplit } // end for PTE } // end for PDE @@ -577,7 +579,7 @@ InitPaging ( // continue; } - Pde =3D (UINT64 *)(UINTN)(Pml4[Level1] & PHYSICAL_ADDRESS_MASK); + Pde =3D (UINT64 *)(UINTN)(Pml4[Level1] & ~mAddressEncMask &=20 + PHYSICAL_ADDRESS_MASK); } else { Pde =3D (UINT64*)(UINTN)mSmmProfileCr3; } @@ -597,7 +599,7 @@ InitPaging ( } continue; } - Pte =3D (UINT64 *)(UINTN)(*Pde & PHYSICAL_ADDRESS_MASK); + Pte =3D (UINT64 *)(UINTN)(*Pde & ~mAddressEncMask &=20 + PHYSICAL_ADDRESS_MASK); if (Pte =3D=3D 0) { continue; } @@ -624,7 +626,7 @@ InitPaging ( } } else { // 4KB page - Pt =3D (UINT64 *)(UINTN)(*Pte & PHYSICAL_ADDRESS_MASK); + Pt =3D (UINT64 *)(UINTN)(*Pte & ~mAddressEncMask &=20 + PHYSICAL_ADDRESS_MASK); if (Pt =3D=3D 0) { continue; } diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuD= xeSmm/X64/PageTbl.c index 17b2f4c..19b19d8 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -2,6 +2,8 @@ Page Fault (#PF) handler for X64 processors =20 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made availab= le under the terms and conditions of the BSD License which accompanies thi= s distribution. The full text of the license may be found at @@ -16,6 +18,= 7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED. =20 #define PAGE_TABLE_PAGES 8 #define ACC_MAX_BIT BIT3 + LIST_ENTRY mPagePool =3D INITIALIZE_LIST_HEAD_VAR= IABLE (mPagePool); BOOLEAN m1GPageTableSupport =3D FALSE; UINT8 mPhysicalAddressBits; @@ -168,13 +171,13 @@ SetStaticPageTable ( // // Each PML4 entry points to a page of Page Directory Pointer entries. // - PageDirectoryPointerEntry =3D (UINT64 *) ((*PageMapLevel4Entry) & gPhy= Mask); + PageDirectoryPointerEntry =3D (UINT64 *) ((*PageMapLevel4Entry) &=20 + ~mAddressEncMask & gPhyMask); if (PageDirectoryPointerEntry =3D=3D NULL) { PageDirectoryPointerEntry =3D AllocatePageTableMemory (1); ASSERT(PageDirectoryPointerEntry !=3D NULL); ZeroMem (PageDirectoryPointerEntry, EFI_PAGES_TO_SIZE(1)); =20 - *PageMapLevel4Entry =3D ((UINTN)PageDirectoryPointerEntry & gPhyMask= ) | PAGE_ATTRIBUTE_BITS; + *PageMapLevel4Entry =3D (UINT64)(UINTN)PageDirectoryPointerEntry |=20 + mAddressEncMask | PAGE_ATTRIBUTE_BITS; } =20 if (m1GPageTableSupport) { @@ -189,7 +192,7 @@ SetStaticPageTable ( // // Fill in the Page Directory entries // - *PageDirectory1GEntry =3D (PageAddress & gPhyMask) | IA32_PG_PS | = PAGE_ATTRIBUTE_BITS; + *PageDirectory1GEntry =3D PageAddress | mAddressEncMask |=20 + IA32_PG_PS | PAGE_ATTRIBUTE_BITS; } } else { PageAddress =3D BASE_4GB; @@ -204,7 +207,7 @@ SetStaticPageTable ( // Each Directory Pointer entries points to a page of Page Directo= ry entires. // So allocate space for them and fill them in in the IndexOfPageD= irectoryEntries loop. // - PageDirectoryEntry =3D (UINT64 *) ((*PageDirectoryPointerEntry) & = gPhyMask); + PageDirectoryEntry =3D (UINT64 *) ((*PageDirectoryPointerEntry) &= =20 + ~mAddressEncMask & gPhyMask); if (PageDirectoryEntry =3D=3D NULL) { PageDirectoryEntry =3D AllocatePageTableMemory (1); ASSERT(PageDirectoryEntry !=3D NULL); @@ -213,14 +216,14 @@ SetS= taticPageTable ( // // Fill in a Page Directory Pointer Entries // - *PageDirectoryPointerEntry =3D (UINT64)(UINTN)PageDirectoryEntry= | PAGE_ATTRIBUTE_BITS; + *PageDirectoryPointerEntry =3D=20 + (UINT64)(UINTN)PageDirectoryEntry | mAddressEncMask |=20 + PAGE_ATTRIBUTE_BITS; } =20 for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntrie= s < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += =3D SIZE_2MB) { // // Fill in the Page Directory entries // - *PageDirectoryEntry =3D (UINT64)PageAddress | IA32_PG_PS | PAGE_= ATTRIBUTE_BITS; + *PageDirectoryEntry =3D PageAddress | mAddressEncMask |=20 + IA32_PG_PS | PAGE_ATTRIBUTE_BITS; } } } @@ -276,7 +279,7 @@ SmmInitPageTable ( // PTEntry =3D (UINT64*)AllocatePageTableMemory (1); ASSERT (PTEntry !=3D NULL); - *PTEntry =3D Pages | PAGE_ATTRIBUTE_BITS; + *PTEntry =3D Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS; ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry)); =20 // @@ -457,7 +460,7 @@ ReclaimPages ( // continue; } - Pdpt =3D (UINT64*)(UINTN)(Pml4[Pml4Index] & gPhyMask); + Pdpt =3D (UINT64*)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask &=20 + gPhyMask); PML4EIgnore =3D FALSE; for (PdptIndex =3D 0; PdptIndex < EFI_PAGE_SIZE / sizeof (*Pdpt); Pdpt= Index++) { if ((Pdpt[PdptIndex] & IA32_PG_P) =3D=3D 0 || (Pdpt[PdptIndex] & IA3= 2_PG_PMNT) !=3D 0) { @@ -478,7 +481,7 @@ ReclaimPages ( // we will not check PML4 entry more // PML4EIgnore =3D TRUE; - Pdt =3D (UINT64*)(UINTN)(Pdpt[PdptIndex] & gPhyMask); + Pdt =3D (UINT64*)(UINTN)(Pdpt[PdptIndex] & ~mAddressEncMask &=20 + gPhyMask); PDPTEIgnore =3D FALSE; for (PdtIndex =3D 0; PdtIndex < EFI_PAGE_SIZE / sizeof(*Pdt); PdtI= ndex++) { if ((Pdt[PdtIndex] & IA32_PG_P) =3D=3D 0 || (Pdt[PdtIndex] & IA3= 2_PG_PMNT) !=3D 0) { @@ -560,7 +563,7 @@ ReclaimPages ( // // Secondly, insert the page pointed by this entry into page pool and cl= ear this entry // - InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(*ReleasePageAddress & g= PhyMask)); + InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(*ReleasePageAddress=20 + & ~mAddressEncMask & gPhyMask)); *ReleasePageAddress =3D 0; =20 // @@ -572,14 +575,14 @@ ReclaimPages ( // // If 4 KByte Page Table is released, check the PDPT entry // - Pdpt =3D (UINT64*)(UINTN)(Pml4[MinPml4] & gPhyMask); + Pdpt =3D (UINT64*)(UINTN)(Pml4[MinPml4] & ~mAddressEncMask &=20 + gPhyMask); SubEntriesNum =3D GetSubEntriesNum(Pdpt + MinPdpt); if (SubEntriesNum =3D=3D 0) { // // Release the empty Page Directory table if there was no more 4 K= Byte Page Table entry // clear the Page directory entry // - InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(Pdpt[MinPdpt] & g= PhyMask)); + InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(Pdpt[MinPdpt]=20 + & ~mAddressEncMask & gPhyMask)); Pdpt[MinPdpt] =3D 0; // // Go on checking the PML4 table @@ -603,7 +606,7 @@ ReclaimPages = ( // Release the empty PML4 table if there was no more 1G KByte Page= Table entry // clear the Page directory entry // - InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(Pml4[MinPml4] & g= PhyMask)); + InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(Pml4[MinPml4]=20 + & ~mAddressEncMask & gPhyMask)); Pml4[MinPml4] =3D 0; MinPdpt =3D (UINTN)-1; continue; @@ -747,7 +750,7 @@ SmiDefaultPFHandler ( // // If the entry is not present, allocate one page from page pool f= or it // - PageTable[PTIndex] =3D AllocPage () | PAGE_ATTRIBUTE_BITS; + PageTable[PTIndex] =3D AllocPage () | mAddressEncMask |=20 + PAGE_ATTRIBUTE_BITS; } else { // // Save the upper entry address @@ -760,7 +763,7 @@ SmiDefaultPFHa= ndler ( // PageTable[PTIndex] |=3D (UINT64)IA32_PG_A; SetAccNum (PageTable + PTIndex, 7); - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask); + PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] &=20 + ~mAddressEncMask & gPhyMask); } =20 PTIndex =3D BitFieldRead64 (PFAddress, StartBit, StartBit + 8); @@ -77= 6,7 +779,7 @@ SmiDefaultPFHandler ( // // Fill the new entry // - PageTable[PTIndex] =3D (PFAddress & gPhyMask & ~((1ull << EndBit) - 1)= ) | + PageTable[PTIndex] =3D ((PFAddress | mAddressEncMask) & gPhyMask &=20 + ~((1ull << EndBit) - 1)) | PageAttribute | IA32_PG_A | PAGE_ATTRIBUTE_BITS; if (UpperEntry !=3D NULL) { SetSubEntriesNum (UpperEntry, GetSubEntriesNum (UpperEntry) + 1); @@= -927,7 +930,7 @@ SetPageTableAttributes ( PageTableSplitted =3D (PageTableSplitted || IsSplitted); =20 for (Index4 =3D 0; Index4 < SIZE_4KB/sizeof(UINT64); Index4++) { - L3PageTable =3D (UINT64 *)(UINTN)(L4PageTable[Index4] & PAGING_4K_AD= DRESS_MASK_64); + L3PageTable =3D (UINT64 *)(UINTN)(L4PageTable[Index4] &=20 + ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); if (L3PageTable =3D=3D NULL) { continue; } @@ -940,7 +943,7 @@ SetPageTableAttributes ( // 1G continue; } - L2PageTable =3D (UINT64 *)(UINTN)(L3PageTable[Index3] & PAGING_4K_= ADDRESS_MASK_64); + L2PageTable =3D (UINT64 *)(UINTN)(L3PageTable[Index3] &=20 + ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); if (L2PageTable =3D=3D NULL) { continue; } @@ -953,7 +956,7 @@ SetPageTableAttributes ( // 2M continue; } - L1PageTable =3D (UINT64 *)(UINTN)(L2PageTable[Index2] & PAGING_4= K_ADDRESS_MASK_64); + L1PageTable =3D (UINT64 *)(UINTN)(L2PageTable[Index2] &=20 + ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); if (L1PageTable =3D=3D NULL) { continue; } diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c b/UefiCpuPkg/Pi= SmmCpuDxeSmm/X64/SmmProfileArch.c index cc393dc..37da5fb 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c @@ -2,6 +2,8 @@ X64 processor specific functions to enable SMM profile. =20 Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made availab= le under the terms and conditions of the BSD License which accompanies thi= s distribution. The full text of the license may be found at @@ -52,7 +54,= 7 @@ InitSmmS3Cr3 ( // PTEntry =3D (UINT64*)AllocatePageTableMemory (1); ASSERT (PTEntry !=3D NULL); - *PTEntry =3D Pages | PAGE_ATTRIBUTE_BITS; + *PTEntry =3D Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS; ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry)); =20 // @@ -111,14 +113,14 @@ AcquirePage ( // // Cut the previous uplink if it exists and wasn't overwritten // - if ((mPFPageUplink[mPFPageIndex] !=3D NULL) && ((*mPFPageUplink[mPFPageI= ndex] & PHYSICAL_ADDRESS_MASK) =3D=3D Address)) { + if ((mPFPageUplink[mPFPageIndex] !=3D NULL) &&=20 + ((*mPFPageUplink[mPFPageIndex] & ~mAddressEncMask &=20 + PHYSICAL_ADDRESS_MASK) =3D=3D Address)) { *mPFPageUplink[mPFPageIndex] =3D 0; } =20 // // Link & Record the current uplink // - *Uplink =3D Address | PAGE_ATTRIBUTE_BITS; + *Uplink =3D Address | mAddressEncMask | PAGE_ATTRIBUTE_BITS; mPFPageUplink[mPFPageIndex] =3D Uplink; =20 mPFPageIndex =3D (mPFPageIndex + 1) % MAX_PF_PAGE_COUNT; @@ -168,33 +170= ,33 @@ RestorePageTableAbove4G ( PTIndex =3D BitFieldRead64 (PFAddress, 39, 47); if ((PageTable[PTIndex] & IA32_PG_P) !=3D 0) { // PML4E - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_M= ASK); + PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask=20 + & PHYSICAL_ADDRESS_MASK); PTIndex =3D BitFieldRead64 (PFAddress, 30, 38); if ((PageTable[PTIndex] & IA32_PG_P) !=3D 0) { // PDPTE - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS= _MASK); + PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] &=20 + ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); PTIndex =3D BitFieldRead64 (PFAddress, 21, 29); // PD if ((PageTable[PTIndex] & IA32_PG_PS) !=3D 0) { // // 2MB page // - Address =3D (UINT64)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK); - if ((Address & PHYSICAL_ADDRESS_MASK & ~((1ull << 21) - 1)) =3D=3D= ((PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 21) - 1)))) { + Address =3D (UINT64)(PageTable[PTIndex] & ~mAddressEncMask & PHYSI= CAL_ADDRESS_MASK); + if ((Address & ~((1ull << 21) - 1)) =3D=3D ((PFAddress &=20 + PHYSICAL_ADDRESS_MASK & ~((1ull << 21) - 1)))) { Existed =3D TRUE; } } else { // // 4KB page // - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRE= SS_MASK); + PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] &=20 + ~mAddressEncMask& PHYSICAL_ADDRESS_MASK); if (PageTable !=3D 0) { // // When there is a valid entry to map to 4KB page, need not crea= te a new entry to map 2MB. // PTIndex =3D BitFieldRead64 (PFAddress, 12, 20); - Address =3D (UINT64)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK)= ; - if ((Address & PHYSICAL_ADDRESS_MASK & ~((1ull << 12) - 1)) =3D= =3D (PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 12) - 1))) { + Address =3D (UINT64)(PageTable[PTIndex] & ~mAddressEncMask & PHY= SICAL_ADDRESS_MASK); + if ((Address & ~((1ull << 12) - 1)) =3D=3D (PFAddress &=20 + PHYSICAL_ADDRESS_MASK & ~((1ull << 12) - 1))) { Existed =3D TRUE; } } @@ -227,13 +229,13 @@ RestorePageTableAbove4G ( PFAddress =3D AsmReadCr2 (); // PML4E PTIndex =3D BitFieldRead64 (PFAddress, 39, 47); - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_M= ASK); + PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask=20 + & PHYSICAL_ADDRESS_MASK); // PDPTE PTIndex =3D BitFieldRead64 (PFAddress, 30, 38); - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_M= ASK); + PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask=20 + & PHYSICAL_ADDRESS_MASK); // PD PTIndex =3D BitFieldRead64 (PFAddress, 21, 29); - Address =3D PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK; + Address =3D PageTable[PTIndex] & ~mAddressEncMask &=20 + PHYSICAL_ADDRESS_MASK; // // Check if 2MB-page entry need be changed to 4KB-page entry. // @@ -241,9 +243,9 @@ RestorePageTableAbove4G ( AcquirePage (&PageTable[PTIndex]); =20 // PTE - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS= _MASK); + PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] &=20 + ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); for (Index =3D 0; Index < 512; Index++) { - PageTable[Index] =3D Address | PAGE_ATTRIBUTE_BITS; + PageTable[Index] =3D Address | mAddressEncMask |=20 + PAGE_ATTRIBUTE_BITS; if (!IsAddressValid (Address, &Nx)) { PageTable[Index] =3D PageTable[Index] & (INTN)(INT32)(~PAGE_ATTR= IBUTE_BITS); } -- 2.7.4