From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4349A82215 for ; Thu, 2 Mar 2017 22:53:27 -0800 (PST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Mar 2017 22:53:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,235,1484035200"; d="scan'208";a="940125645" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga003.jf.intel.com with ESMTP; 02 Mar 2017 22:53:22 -0800 Received: from fmsmsx125.amr.corp.intel.com (10.18.125.40) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 2 Mar 2017 22:53:21 -0800 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by FMSMSX125.amr.corp.intel.com (10.18.125.40) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 2 Mar 2017 22:53:20 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.88]) by SHSMSX103.ccr.corp.intel.com ([10.239.4.69]) with mapi id 14.03.0248.002; Fri, 3 Mar 2017 14:53:19 +0800 From: "Fan, Jeff" To: Leo Duran , "edk2-devel@ml01.01.org" CC: "Tian, Feng" , "Zeng, Star" , Laszlo Ersek , Brijesh Singh Thread-Topic: [PATCH] UefiCpuPkg/CpuDxe: Add support for PCD PcdPteMemoryEncryptionAddressOrMask Thread-Index: AQHSk63MkAiCzb221kiCjeiM9s2FKqGCrcVg Date: Fri, 3 Mar 2017 06:53:18 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C5515E6@shsmsx102.ccr.corp.intel.com> References: <1488497763-10435-1-git-send-email-leo.duran@amd.com> <1488497763-10435-2-git-send-email-leo.duran@amd.com> In-Reply-To: <1488497763-10435-2-git-send-email-leo.duran@amd.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYjE0ZmE4MWEtYmMxMC00ODVjLWFjZmQtNTA4NzdmZTYxYTljIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6Ikx4eFhjMXhMSDh3MlZBdVN5Y3pqRkRKWGhmdHNYOFhDZEgrdFY4b1dQNnM9In0= x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] UefiCpuPkg/CpuDxe: Add support for PCD PcdPteMemoryEncryptionAddressOrMask X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 03 Mar 2017 06:53:27 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jeff Fan -----Original Message----- From: Leo Duran [mailto:leo.duran@amd.com]=20 Sent: Friday, March 03, 2017 7:36 AM To: edk2-devel@ml01.01.org Cc: Leo Duran; Fan, Jeff; Tian, Feng; Zeng, Star; Laszlo Ersek; Brijesh Sin= gh Subject: [PATCH] UefiCpuPkg/CpuDxe: Add support for PCD PcdPteMemoryEncrypt= ionAddressOrMask This PCD holds the address mask for page table entries when memory encrypti= on is enabled on AMD processors supporting the Secure Encrypted Virtualizat= ion (SEV) feature. The mask is applied when page tables entries are created or modified. CC: Jeff Fan Cc: Feng Tian Cc: Star Zeng Cc: Laszlo Ersek Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran --- UefiCpuPkg/CpuDxe/CpuDxe.inf | 5 +++++ UefiCpuPkg/CpuDxe/CpuPageTable.c | 30 +++++++++++++++++++++--------- 2 files changed, 26 insertions(+), 9 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf in= dex e568ceb..ec535e8 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf @@ -2,6 +2,8 @@ # CPU driver installs CPU Architecture Protocol and CPU MP protocol. # # Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# # This program and the accompanying materials # are licensed and made a= vailable under the terms and conditions of the BSD License # which accomp= anies this distribution. The full text of the license may be found at @@ -= 77,6 +79,9 @@ gEfiSecPlatformInformation2PpiGuid ## UNDEFINED # HOB gEfiSecPlatformInformationPpiGuid ## UNDEFINED # HOB =20 + [Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask #= # CONSUMES + [Depex] TRUE =20 diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTa= ble.c index 202d1d9..65f607a 100644 --- a/UefiCpuPkg/CpuDxe/CpuPageTable.c +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c @@ -2,6 +2,8 @@ Page table management support. =20 Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -271,6 +273,7 @@ GetPageTableEntry ( UINT64 *L2PageTable; UINT64 *L3PageTable; UINT64 *L4PageTable; + UINT64 AddressEncMask; =20 ASSERT (PagingContext !=3D NULL); =20 @@ -279,6 +282,10 @@ GetPageTableEntry ( Index2 =3D ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK; Index1 =3D ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK; =20 + // Make sure AddressEncMask is contained to smallest supported address f= ield. + // + AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &=20 + PAGING_1G_ADDRESS_MASK_64; + if (PagingContext->MachineType =3D=3D IMAGE_FILE_MACHINE_X64) { L4PageTable =3D (UINT64 *)(UINTN)PagingContext->ContextData.X64.PageTa= bleBase; if (L4PageTable[Index4] =3D=3D 0) { @@ -286,7 +293,7 @@ GetPageTableEntry ( return NULL; } =20 - L3PageTable =3D (UINT64 *)(UINTN)(L4PageTable[Index4] & PAGING_4K_ADDR= ESS_MASK_64); + L3PageTable =3D (UINT64 *)(UINTN)(L4PageTable[Index4] &=20 + ~AddressEncMask & PAGING_4K_ADDRESS_MASK_64); } else { ASSERT((PagingContext->ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PA= GING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) !=3D 0); L3PageTable =3D (UINT64 *)(UINTN)PagingContext->ContextData.Ia32.PageT= ableBase; @@ -301,7 +308,7 @@ GetPageTableEntry ( return &L3PageTable[Index3]; } =20 - L2PageTable =3D (UINT64 *)(UINTN)(L3PageTable[Index3] & PAGING_4K_ADDRES= S_MASK_64); + L2PageTable =3D (UINT64 *)(UINTN)(L3PageTable[Index3] & ~AddressEncMask= =20 + & PAGING_4K_ADDRESS_MASK_64); if (L2PageTable[Index2] =3D=3D 0) { *PageAttribute =3D PageNone; return NULL; @@ -313,7 +320,7 @@ GetPageTableEntry ( } =20 // 4k - L1PageTable =3D (UINT64 *)(UINTN)(L2PageTable[Index2] & PAGING_4K_ADDRES= S_MASK_64); + L1PageTable =3D (UINT64 *)(UINTN)(L2PageTable[Index2] & ~AddressEncMask= =20 + & PAGING_4K_ADDRESS_MASK_64); if ((L1PageTable[Index1] =3D=3D 0) && (Address !=3D 0)) { *PageAttribute =3D PageNone; return NULL; @@ -499,11 +506,16 @@ SplitPage ( UINT64 BaseAddress; UINT64 *NewPageEntry; UINTN Index; + UINT64 AddressEncMask; =20 ASSERT (PageAttribute =3D=3D Page2M || PageAttribute =3D=3D Page1G); =20 ASSERT (AllocatePagesFunc !=3D NULL); =20 + // Make sure AddressEncMask is contained to smallest supported address f= ield. + // + AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &=20 + PAGING_1G_ADDRESS_MASK_64; + if (PageAttribute =3D=3D Page2M) { // // Split 2M to 4K @@ -515,11 +527,11 @@ SplitPage ( if (NewPageEntry =3D=3D NULL) { return RETURN_OUT_OF_RESOURCES; } - BaseAddress =3D *PageEntry & PAGING_2M_ADDRESS_MASK_64; + BaseAddress =3D *PageEntry & ~AddressEncMask &=20 + PAGING_2M_ADDRESS_MASK_64; for (Index =3D 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { - NewPageEntry[Index] =3D BaseAddress + SIZE_4KB * Index + ((*PageEn= try) & PAGE_PROGATE_BITS); + NewPageEntry[Index] =3D (BaseAddress + SIZE_4KB * Index) |=20 + AddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS); } - (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry + ((*PageEntry) & PAGE_= PROGATE_BITS); + (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry | AddressEncMask |=20 + ((*PageEntry) & PAGE_PROGATE_BITS); return RETURN_SUCCESS; } else { return RETURN_UNSUPPORTED; @@ -536,11 +548,11 @@ SplitPage ( if (NewPageEntry =3D=3D NULL) { return RETURN_OUT_OF_RESOURCES; } - BaseAddress =3D *PageEntry & PAGING_1G_ADDRESS_MASK_64; + BaseAddress =3D *PageEntry & ~AddressEncMask &=20 + PAGING_1G_ADDRESS_MASK_64; for (Index =3D 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { - NewPageEntry[Index] =3D BaseAddress + SIZE_2MB * Index + IA32_PG_P= S + ((*PageEntry) & PAGE_PROGATE_BITS); + NewPageEntry[Index] =3D (BaseAddress + SIZE_2MB * Index) |=20 + AddressEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS); } - (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry + ((*PageEntry) & PAGE_= PROGATE_BITS); + (*PageEntry) =3D (UINT64)(UINTN)NewPageEntry | AddressEncMask |=20 + ((*PageEntry) & PAGE_PROGATE_BITS); return RETURN_SUCCESS; } else { return RETURN_UNSUPPORTED; -- 2.7.4