Re: [PATCH V4 1/3] UefiCpuPkg/CpuDxe: Add memory attribute setting.

["Fan, Jeff" <jeff.fan@intel.com>]

Anthony,

It's very interesting.  Some INTEL IA-32 architectural MSR (like 0x1A0, IA32_MISC_ENABLE) is not supported by AMD processors.

For this case, I think reading 0x1A0 is not necessary. Reading CPUID.80000001H:EDK[20] is enough to check if XD feature is supported or not.

I will create the patch to remove the following check.

      if ((AsmReadMsr64 (0x000001A0) & BIT34) == 0) {
        // XD enabled

I suggest to review such issue case by case when we encounter unsupported architectural MSRs on AMD processors in the future.

Thanks!
Jeff

-----Original Message-----
From: Anthony PERARD [mailto:anthony.perard@citrix.com] 
Sent: Friday, March 10, 2017 11:22 PM
To: Fan, Jeff
Cc: Yao, Jiewen; edk2-devel@lists.01.org; Kinney, Michael D
Subject: Re: [edk2] [PATCH V4 1/3] UefiCpuPkg/CpuDxe: Add memory attribute setting.

On Fri, Mar 10, 2017 at 01:02:22AM +0000, Fan, Jeff wrote:
> Anthony,
> 
> MSR 0x1A0 is architectural MSR defined in IA32 SDM.
> 
> Have you tried AMD real platform?

Yes, I did, and unless I've made a mistake, trying to read msr 0x1a0 does generate a GPF.

Also, I've now take a look into the AMD manuals[1] and more specificaly
"AMD64 Architecture Programmer’s Manual Volume 2: System Programming"[2], there is no sign of MSR 0x1a0 (in Appendix A).

As for the XD bit on AMD, (well NX actually), it is describe at 5.6.3, in the "Page Translation and Protection" chapter.


About MSR 0x1a0 been architectural defined, I guess that applies only to Intel CPUs, all of them.

[1]: http://developer.amd.com/resources/developer-guides-manuals/
[2]: http://support.amd.com/TechDocs/24593.pdf

Thanks,

--
Anthony PERARD