[PATCH] UefiCpuPkg/PiSmmCpuDxeSmm:

[PATCH] UefiCpuPkg/PiSmmCpuDxeSmm:

[Leo Duran]

This PCD holds the address mask for page table entries when memory
encryption is enabled on AMD processors supporting the Secure Encrypted
Virtualization (SEV) feature.

The mask is applied when page tables entries are created or modified.
This patch removes the SEV mask on addresses from page-table entries.

This patch follows [PATCH v4 0/6] Add PCD PcdPteMemoryEncryptionAddressOrMask
which has alreeady being pushed upstream.

Leo Duran (1):
  UefiCpuPkg/PiSmmCpuDxeSmm:     Bug-Fix for supporting PCD
    PcdPteMemoryEncryptionAddressOrMask

 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

-- 
2.7.4

[PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Bug-Fix for supporting PCD PcdPteMemoryEncryptionAddressOrMask

[Leo Duran]

This PCD holds the address mask for page table entries when memory
encryption is enabled on AMD processors supporting the Secure Encrypted
Virtualization (SEV) feature.

The mask is applied when page tables entries are created or modified.
This patch removes the SEV mask on addresses from page-table entries.

CC: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
---
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
index a535389..cb415d3 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
@@ -1,6 +1,8 @@
 /** @file
 
 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+
 This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD License
 which accompanies this distribution.  The full text of the license may be found at
@@ -302,7 +304,7 @@ SplitPage (
       if (NewPageEntry == NULL) {
         return RETURN_OUT_OF_RESOURCES;
       }
-      BaseAddress = *PageEntry & PAGING_2M_ADDRESS_MASK_64;
+      BaseAddress = *PageEntry & ~mAddressEncMask & PAGING_2M_ADDRESS_MASK_64;
       for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {
         NewPageEntry[Index] = (BaseAddress + SIZE_4KB * Index) | mAddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS);
       }
@@ -323,7 +325,7 @@ SplitPage (
       if (NewPageEntry == NULL) {
         return RETURN_OUT_OF_RESOURCES;
       }
-      BaseAddress = *PageEntry & PAGING_1G_ADDRESS_MASK_64;
+      BaseAddress = *PageEntry & ~mAddressEncMask & PAGING_1G_ADDRESS_MASK_64;
       for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {
         NewPageEntry[Index] = (BaseAddress + SIZE_2MB * Index) | mAddressEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS);
       }
-- 
2.7.4

Re: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Bug-Fix for supporting PCD PcdPteMemoryEncryptionAddressOrMask

[Fan, Jeff]

Reviewed-by: Jeff Fan <jeff.fan@intel.com>

-----Original Message-----
From: Leo Duran [mailto:leo.duran@amd.com] 
Sent: Wednesday, March 15, 2017 5:13 AM
To: edk2-devel@ml01.01.org
Cc: Leo Duran; Fan, Jeff; Tian, Feng; Zeng, Star; Laszlo Ersek; Brijesh Singh
Subject: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Bug-Fix for supporting PCD PcdPteMemoryEncryptionAddressOrMask

This PCD holds the address mask for page table entries when memory encryption is enabled on AMD processors supporting the Secure Encrypted Virtualization (SEV) feature.

The mask is applied when page tables entries are created or modified.
This patch removes the SEV mask on addresses from page-table entries.

CC: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
---
 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
index a535389..cb415d3 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
@@ -1,6 +1,8 @@
 /** @file
 
 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+
 This program and the accompanying materials  are licensed and made available under the terms and conditions of the BSD License  which accompanies this distribution.  The full text of the license may be found at @@ -302,7 +304,7 @@ SplitPage (
       if (NewPageEntry == NULL) {
         return RETURN_OUT_OF_RESOURCES;
       }
-      BaseAddress = *PageEntry & PAGING_2M_ADDRESS_MASK_64;
+      BaseAddress = *PageEntry & ~mAddressEncMask & 
+ PAGING_2M_ADDRESS_MASK_64;
       for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {
         NewPageEntry[Index] = (BaseAddress + SIZE_4KB * Index) | mAddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS);
       }
@@ -323,7 +325,7 @@ SplitPage (
       if (NewPageEntry == NULL) {
         return RETURN_OUT_OF_RESOURCES;
       }
-      BaseAddress = *PageEntry & PAGING_1G_ADDRESS_MASK_64;
+      BaseAddress = *PageEntry & ~mAddressEncMask & 
+ PAGING_1G_ADDRESS_MASK_64;
       for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {
         NewPageEntry[Index] = (BaseAddress + SIZE_2MB * Index) | mAddressEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS);
       }
--
2.7.4