From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 52A9D802E6 for ; Tue, 14 Mar 2017 18:57:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1489543049; x=1521079049; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=Phrh1t2AKAb7YZpKmK0P7cDrjwkgwfuVHNrNUuvQ+DQ=; b=dO9WYAm3nFExIr6bIbrdIzuDuEJLj8SLYGob4jfIW/nIFOUOLwez6GeY TU8XV23qPrp5sRsWdtRTBRjm1tWzsw==; Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Mar 2017 18:57:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,166,1486454400"; d="scan'208";a="944382697" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga003.jf.intel.com with ESMTP; 14 Mar 2017 18:57:28 -0700 Received: from fmsmsx156.amr.corp.intel.com (10.18.116.74) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 14 Mar 2017 18:57:27 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx156.amr.corp.intel.com (10.18.116.74) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 14 Mar 2017 18:57:27 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.88]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.177]) with mapi id 14.03.0248.002; Wed, 15 Mar 2017 09:57:25 +0800 From: "Fan, Jeff" To: Leo Duran , "edk2-devel@ml01.01.org" CC: "Tian, Feng" , "Zeng, Star" , Laszlo Ersek , Brijesh Singh Thread-Topic: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Bug-Fix for supporting PCD PcdPteMemoryEncryptionAddressOrMask Thread-Index: AQHSnQfDCJxn80WKvUKcpz6nF97dOKGVJMWQ Date: Wed, 15 Mar 2017 01:57:24 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C5602E3@shsmsx102.ccr.corp.intel.com> References: <1489525954-30988-1-git-send-email-leo.duran@amd.com> <1489525954-30988-2-git-send-email-leo.duran@amd.com> In-Reply-To: <1489525954-30988-2-git-send-email-leo.duran@amd.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYzA1ZmU3MWQtODk5OC00NjAyLThmMmUtYmE0OTc3MjBiZmQ0IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IkdaZDFoMHl4Ym12QnlRQ3B5VG5YNUl5cGJxV3BNajZuMjBqT010dmdOVG89In0= x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Bug-Fix for supporting PCD PcdPteMemoryEncryptionAddressOrMask X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Mar 2017 01:57:29 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jeff Fan -----Original Message----- From: Leo Duran [mailto:leo.duran@amd.com]=20 Sent: Wednesday, March 15, 2017 5:13 AM To: edk2-devel@ml01.01.org Cc: Leo Duran; Fan, Jeff; Tian, Feng; Zeng, Star; Laszlo Ersek; Brijesh Sin= gh Subject: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Bug-Fix for supporting PCD PcdP= teMemoryEncryptionAddressOrMask This PCD holds the address mask for page table entries when memory encrypti= on is enabled on AMD processors supporting the Secure Encrypted Virtualizat= ion (SEV) feature. The mask is applied when page tables entries are created or modified. This patch removes the SEV mask on addresses from page-table entries. CC: Jeff Fan Cc: Feng Tian Cc: Star Zeng Cc: Laszlo Ersek Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran --- UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPk= g/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index a535389..cb415d3 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -1,6 +1,8 @@ /** @file =20 Copyright (c) 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made availab= le under the terms and conditions of the BSD License which accompanies thi= s distribution. The full text of the license may be found at @@ -302,7 +30= 4,7 @@ SplitPage ( if (NewPageEntry =3D=3D NULL) { return RETURN_OUT_OF_RESOURCES; } - BaseAddress =3D *PageEntry & PAGING_2M_ADDRESS_MASK_64; + BaseAddress =3D *PageEntry & ~mAddressEncMask &=20 + PAGING_2M_ADDRESS_MASK_64; for (Index =3D 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { NewPageEntry[Index] =3D (BaseAddress + SIZE_4KB * Index) | mAddres= sEncMask | ((*PageEntry) & PAGE_PROGATE_BITS); } @@ -323,7 +325,7 @@ SplitPage ( if (NewPageEntry =3D=3D NULL) { return RETURN_OUT_OF_RESOURCES; } - BaseAddress =3D *PageEntry & PAGING_1G_ADDRESS_MASK_64; + BaseAddress =3D *PageEntry & ~mAddressEncMask &=20 + PAGING_1G_ADDRESS_MASK_64; for (Index =3D 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { NewPageEntry[Index] =3D (BaseAddress + SIZE_2MB * Index) | mAddres= sEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS); } -- 2.7.4