From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C6AAB803B7 for ; Thu, 23 Mar 2017 00:42:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490254935; x=1521790935; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=/mpPZdr7mJZg6eDedG9gmeIIwRkhDYd7Hy/rBr5kBbU=; b=Sjj5SVL42YMn8I+kgtEVDEistQjnip9/BP6sX3BFJw4B0CKPS3dRMdt8 QnPiuQXD6H2ZP2sah88vgcTQvxadMw==; Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Mar 2017 00:42:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,208,1486454400"; d="scan'208";a="837681768" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by FMSMGA003.fm.intel.com with ESMTP; 23 Mar 2017 00:42:15 -0700 Received: from fmsmsx123.amr.corp.intel.com (10.18.125.38) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 23 Mar 2017 00:42:15 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx123.amr.corp.intel.com (10.18.125.38) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 23 Mar 2017 00:42:14 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.88]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.132]) with mapi id 14.03.0248.002; Thu, 23 Mar 2017 15:42:12 +0800 From: "Fan, Jeff" To: Laszlo Ersek , Brijesh Singh , "Kinney, Michael D" , "Justen, Jordan L" , "edk2-devel@ml01.01.org" , "Gao, Liming" CC: "leo.duran@amd.com" , "brijesh.singh@amd.com" , "Thomas.Lendacky@amd.com" Thread-Topic: [edk2] [RFC PATCH v2 01/10] OvmfPkg/Include: Define SEV specific CPUID and MSR Thread-Index: AQHSoofpt+VCu4Tce0u/TsD9XVsXI6GggJ+AgAGJ7HA= Date: Thu, 23 Mar 2017 07:42:11 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C569A29@shsmsx102.ccr.corp.intel.com> References: <149013076154.27235.10725020825643505862.stgit@brijesh-build-machine> <149013076888.27235.3173588515291478806.stgit@brijesh-build-machine> In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMmMxODAxNzAtZTRjMi00NmViLThiNmQtNWQ1ODE2NjFkMzkwIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6ImdkT0ZONFMrOUxCc29PcnZwYVRKaXNFays2T1BoazIzWjRhM2p2UEVZblk9In0= x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [RFC PATCH v2 01/10] OvmfPkg/Include: Define SEV specific CPUID and MSR X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Mar 2017 07:42:16 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Laszlo, UefiCpuPkg/Include/Register/Cpuid.h defined the CPUID only described in IA3= 2 SDM. UefiCpuPkg/Include/Register/ArchitecturalMsr.h defined the IA32 Architectur= al MSRs in IA32 SDM UefiCpuPkg/Include/Register/Msr/xxxxMsr.h defined the IA32 Model-specific M= SRs in IA32 SDM. I am not sure if Brijesh/Leo has some idea to place SEV specific CPUID/MSRs= definitions. I think one new file or new folder is better. Thanks! Jeff -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Lasz= lo Ersek Sent: Thursday, March 23, 2017 12:04 AM To: Brijesh Singh; Kinney, Michael D; Justen, Jordan L; edk2-devel@ml01.01.= org; Gao, Liming; Fan, Jeff Cc: leo.duran@amd.com; brijesh.singh@amd.com; Thomas.Lendacky@amd.com Subject: Re: [edk2] [RFC PATCH v2 01/10] OvmfPkg/Include: Define SEV specif= ic CPUID and MSR Adding Jeff On 03/21/17 22:12, Brijesh Singh wrote: > The patch defines AMD's Memory Encryption Information CPUID leaf (0x8000_= 001F). > The complete description for this CPUID leaf is available in APM=20 > volume 2 [1] Section 15.34 (Secure Encrypted Virtualization). >=20 > [1] http://support.amd.com/TechDocs/24593.pdf >=20 > Signed-off-by: Brijesh Singh > --- > OvmfPkg/Include/Register/AmdSevMap.h | 133=20 > ++++++++++++++++++++++++++++++++++ > 1 file changed, 133 insertions(+) > create mode 100644 OvmfPkg/Include/Register/AmdSevMap.h >=20 > diff --git a/OvmfPkg/Include/Register/AmdSevMap.h=20 > b/OvmfPkg/Include/Register/AmdSevMap.h > new file mode 100644 > index 0000000..de80f39 > --- /dev/null > +++ b/OvmfPkg/Include/Register/AmdSevMap.h > @@ -0,0 +1,133 @@ > +/** @file > + > +AMD Secure Encrypted Virtualization (SEV) specific CPUID and MSR=20 > +definitions > + > +The complete description for this CPUID leaf is available in APM=20 > +volume 2 (Section 15.34) http://support.amd.com/TechDocs/24593.pdf > + > +Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
> + > +This program and the accompanying materials are licensed and made=20 > +available under the terms and conditions of the BSD License which=20 > +accompanies this distribution. The full text of the license may be=20 > +found at http://opensource.org/licenses/bsd-license.php > + > +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,=20 > +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. > + > +**/ > + > +#ifndef __AMD_SEV_MAP_H__ > +#define __AMD_SEV_MAP_H__ > + > +#pragma pack (1) > + > +#define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F > + > +/** > + CPUID Memory Encryption support information EAX for CPUID leaf > + #CPUID_MEMORY_ENCRYPTION_INFO. > +**/ > +typedef union { > + /// > + /// Individual bit fields > + /// > + struct { > + /// > + /// [Bit 0] Secure Memory Encryption (Sme) Support > + /// > + UINT32 SmeBit:1; > + > + /// > + /// [Bit 1] Secure Encrypted Virtualization (Sev) Support > + /// > + UINT32 SevBit:1; > + > + /// > + /// [Bit 2] Page flush MSR support > + /// > + UINT32 PageFlushMsrBit:1; > + > + /// > + /// [Bit 3] Encrypted state support > + /// > + UINT32 SevEsBit:1; > + > + /// > + /// [Bit 4:31] Reserved > + /// > + UINT32 ReservedBits:28; > + } Bits; > + /// > + /// All bit fields as a 32-bit value > + /// > + UINT32 Uint32; > +} CPUID_MEMORY_ENCRYPTION_INFO_EAX; > + > +/** > + CPUID Memory Encryption support information EBX for CPUID leaf > + #CPUID_MEMORY_ENCRYPTION_INFO. > +**/ > +typedef union { > + /// > + /// Individual bit fields > + /// > + struct { > + /// > + /// [Bit 0:5] Page table bit number used to enable memory encryption > + /// > + UINT32 PtePosBits:6; > + > + /// > + /// [Bit 6:11] Reduction of system physical address space bits when = memory encryption is enabled > + /// > + UINT32 ReducedPhysBits:5; > + > + /// > + /// [Bit 12:31] Reserved > + /// > + UINT32 ReservedBits:21; > + } Bits; > + /// > + /// All bit fields as a 32-bit value > + /// > + UINT32 Uint32; > +} CPUID_MEMORY_ENCRYPTION_INFO_EBX; > + > +/** > + Secure Encrypted Virtualization (SEV) status register > + > +**/ > +#define MSR_SEV_STATUS 0xc0010131 > + > +/** > + MSR information returned for #MSR_SEV_STATUS **/ typedef union { > + /// > + /// Individual bit fields > + /// > + struct { > + /// > + /// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled > + /// > + UINT32 SevBit:1; > + > + /// > + /// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) = is enabled > + /// > + UINT32 SevEsBit:1; > + > + UINT32 Reserved:30; > + } Bits; > + /// > + /// All bit fields as a 32-bit value > + /// > + UINT32 Uint32; > + /// > + /// All bit fields as a 64-bit value > + /// > + UINT64 Uint64; > +} MSR_SEV_STATUS_REGISTER; > + > +#endif >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel >=20 I feel that these definitions should be added to "UefiCpuPkg/Include/Regist= er/Cpuid.h", or else to another (new) header file in that directory. Jeff, what do you think? Thanks! Laszlo _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel