From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C009321BC6A7F for ; Mon, 27 Mar 2017 00:58:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490601485; x=1522137485; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=fevEiT3/tG7yR2+cUtACCuYsozLVqK8pxW5o7ZXfiw4=; b=GYIufchcS0X7ok72FXUrfm9uNgxf3SWHXpAU7OV2n6kUDksq0BAo58JD PHSF0rY49pixEC5ynVpR1HDISK6aMQ==; Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Mar 2017 00:58:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,229,1486454400"; d="scan'208";a="81323189" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga006.fm.intel.com with ESMTP; 27 Mar 2017 00:58:01 -0700 Received: from fmsmsx124.amr.corp.intel.com (10.18.125.39) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 27 Mar 2017 00:58:01 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by fmsmsx124.amr.corp.intel.com (10.18.125.39) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 27 Mar 2017 00:58:01 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.212]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.253]) with mapi id 14.03.0248.002; Mon, 27 Mar 2017 15:57:59 +0800 From: "Fan, Jeff" To: Laszlo Ersek , Brijesh Singh , "Kinney, Michael D" , "Justen, Jordan L" , "edk2-devel@ml01.01.org" , "Gao, Liming" CC: "leo.duran@amd.com" , "brijesh.singh@amd.com" , "Thomas.Lendacky@amd.com" Thread-Topic: [edk2] [RFC PATCH v2 01/10] OvmfPkg/Include: Define SEV specific CPUID and MSR Thread-Index: AQHSoofpt+VCu4Tce0u/TsD9XVsXI6GggJ+AgAGJ7HD//5dyAIAGtpwg Date: Mon, 27 Mar 2017 07:57:57 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C57C672@shsmsx102.ccr.corp.intel.com> References: <149013076154.27235.10725020825643505862.stgit@brijesh-build-machine> <149013076888.27235.3173588515291478806.stgit@brijesh-build-machine> <542CF652F8836A4AB8DBFAAD40ED192A4C569A29@shsmsx102.ccr.corp.intel.com> In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOTFlMjhlN2YtYzVkZC00YjlkLTg1ZGUtY2UxNjkxNzdiNTVhIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IlJcL2FvTGhrTlQxS2o4aU9paTN6MEhMdWJ5ZFdIZDh5UUI5OTZJeWQxZ1wvbz0ifQ== x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [RFC PATCH v2 01/10] OvmfPkg/Include: Define SEV specific CPUID and MSR X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Mar 2017 07:58:05 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Laszlo, One Amd directory under UefiCpuPkg/Include/Register is better. Does Brijesh/Leo have any comments, or have other suggestions? Thanks! Jeff -----Original Message----- From: Laszlo Ersek [mailto:lersek@redhat.com]=20 Sent: Thursday, March 23, 2017 5:20 PM To: Fan, Jeff; Brijesh Singh; Kinney, Michael D; Justen, Jordan L; edk2-dev= el@ml01.01.org; Gao, Liming Cc: leo.duran@amd.com; brijesh.singh@amd.com; Thomas.Lendacky@amd.com Subject: Re: [edk2] [RFC PATCH v2 01/10] OvmfPkg/Include: Define SEV specif= ic CPUID and MSR On 03/23/17 08:42, Fan, Jeff wrote: > Laszlo, >=20 > UefiCpuPkg/Include/Register/Cpuid.h defined the CPUID only described in I= A32 SDM. > UefiCpuPkg/Include/Register/ArchitecturalMsr.h defined the IA32=20 > Architectural MSRs in IA32 SDM UefiCpuPkg/Include/Register/Msr/xxxxMsr.h = defined the IA32 Model-specific MSRs in IA32 SDM. >=20 > I am not sure if Brijesh/Leo has some idea to place SEV specific CPUID/MS= Rs definitions. > I think one new file or new folder is better. I agree, both would work for me. My main point is that this feature depends= on physical processor attributes, not on emulated (virtual) hardware or on= various hypervisors, plus it is defined in a public industry spec, so it s= eems to belong under UefiCpuPkg, not OvmfPkg. How about UefiCpuPkg/Include/AmdRegister/Cpuid.h UefiCpuPkg/Include/AmdRegister/ArchitecturalMsr.h UefiCpuPkg/Include/AmdRegister/Msr/xxxxMsr.h or else: UefiCpuPkg/Include/Register/Amd/Cpuid.h UefiCpuPkg/Include/Register/Amd/ArchitecturalMsr.h UefiCpuPkg/Include/Register/Amd/Msr/xxxxMsr.h (as appropriate -- I'm not saying that this patch should create all of thes= e files / subdirectories at once). Thanks Laszlo >=20 > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of=20 > Laszlo Ersek > Sent: Thursday, March 23, 2017 12:04 AM > To: Brijesh Singh; Kinney, Michael D; Justen, Jordan L;=20 > edk2-devel@ml01.01.org; Gao, Liming; Fan, Jeff > Cc: leo.duran@amd.com; brijesh.singh@amd.com; Thomas.Lendacky@amd.com > Subject: Re: [edk2] [RFC PATCH v2 01/10] OvmfPkg/Include: Define SEV=20 > specific CPUID and MSR >=20 > Adding Jeff >=20 > On 03/21/17 22:12, Brijesh Singh wrote: >> The patch defines AMD's Memory Encryption Information CPUID leaf (0x8000= _001F). >> The complete description for this CPUID leaf is available in APM=20 >> volume 2 [1] Section 15.34 (Secure Encrypted Virtualization). >> >> [1] http://support.amd.com/TechDocs/24593.pdf >> >> Signed-off-by: Brijesh Singh >> --- >> OvmfPkg/Include/Register/AmdSevMap.h | 133 >> ++++++++++++++++++++++++++++++++++ >> 1 file changed, 133 insertions(+) >> create mode 100644 OvmfPkg/Include/Register/AmdSevMap.h >> >> diff --git a/OvmfPkg/Include/Register/AmdSevMap.h >> b/OvmfPkg/Include/Register/AmdSevMap.h >> new file mode 100644 >> index 0000000..de80f39 >> --- /dev/null >> +++ b/OvmfPkg/Include/Register/AmdSevMap.h >> @@ -0,0 +1,133 @@ >> +/** @file >> + >> +AMD Secure Encrypted Virtualization (SEV) specific CPUID and MSR=20 >> +definitions >> + >> +The complete description for this CPUID leaf is available in APM=20 >> +volume 2 (Section 15.34) http://support.amd.com/TechDocs/24593.pdf >> + >> +Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
>> + >> +This program and the accompanying materials are licensed and made=20 >> +available under the terms and conditions of the BSD License which=20 >> +accompanies this distribution. The full text of the license may be=20 >> +found at http://opensource.org/licenses/bsd-license.php >> + >> +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"=20 >> +BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRES= S OR IMPLIED. >> + >> +**/ >> + >> +#ifndef __AMD_SEV_MAP_H__ >> +#define __AMD_SEV_MAP_H__ >> + >> +#pragma pack (1) >> + >> +#define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F >> + >> +/** >> + CPUID Memory Encryption support information EAX for CPUID leaf >> + #CPUID_MEMORY_ENCRYPTION_INFO. >> +**/ >> +typedef union { >> + /// >> + /// Individual bit fields >> + /// >> + struct { >> + /// >> + /// [Bit 0] Secure Memory Encryption (Sme) Support >> + /// >> + UINT32 SmeBit:1; >> + >> + /// >> + /// [Bit 1] Secure Encrypted Virtualization (Sev) Support >> + /// >> + UINT32 SevBit:1; >> + >> + /// >> + /// [Bit 2] Page flush MSR support >> + /// >> + UINT32 PageFlushMsrBit:1; >> + >> + /// >> + /// [Bit 3] Encrypted state support >> + /// >> + UINT32 SevEsBit:1; >> + >> + /// >> + /// [Bit 4:31] Reserved >> + /// >> + UINT32 ReservedBits:28; >> + } Bits; >> + /// >> + /// All bit fields as a 32-bit value >> + /// >> + UINT32 Uint32; >> +} CPUID_MEMORY_ENCRYPTION_INFO_EAX; >> + >> +/** >> + CPUID Memory Encryption support information EBX for CPUID leaf >> + #CPUID_MEMORY_ENCRYPTION_INFO. >> +**/ >> +typedef union { >> + /// >> + /// Individual bit fields >> + /// >> + struct { >> + /// >> + /// [Bit 0:5] Page table bit number used to enable memory encryptio= n >> + /// >> + UINT32 PtePosBits:6; >> + >> + /// >> + /// [Bit 6:11] Reduction of system physical address space bits when= memory encryption is enabled >> + /// >> + UINT32 ReducedPhysBits:5; >> + >> + /// >> + /// [Bit 12:31] Reserved >> + /// >> + UINT32 ReservedBits:21; >> + } Bits; >> + /// >> + /// All bit fields as a 32-bit value >> + /// >> + UINT32 Uint32; >> +} CPUID_MEMORY_ENCRYPTION_INFO_EBX; >> + >> +/** >> + Secure Encrypted Virtualization (SEV) status register >> + >> +**/ >> +#define MSR_SEV_STATUS 0xc0010131 >> + >> +/** >> + MSR information returned for #MSR_SEV_STATUS **/ typedef union { >> + /// >> + /// Individual bit fields >> + /// >> + struct { >> + /// >> + /// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled >> + /// >> + UINT32 SevBit:1; >> + >> + /// >> + /// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs)= is enabled >> + /// >> + UINT32 SevEsBit:1; >> + >> + UINT32 Reserved:30; >> + } Bits; >> + /// >> + /// All bit fields as a 32-bit value >> + /// >> + UINT32 Uint32; >> + /// >> + /// All bit fields as a 64-bit value >> + /// >> + UINT64 Uint64; >> +} MSR_SEV_STATUS_REGISTER; >> + >> +#endif >> >> _______________________________________________ >> edk2-devel mailing list >> edk2-devel@lists.01.org >> https://lists.01.org/mailman/listinfo/edk2-devel >> >=20 > I feel that these definitions should be added to "UefiCpuPkg/Include/Regi= ster/Cpuid.h", or else to another (new) header file in that directory. >=20 > Jeff, what do you think? >=20 > Thanks! > Laszlo > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel >=20