From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C96B921A16E46 for ; Wed, 10 May 2017 17:30:40 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 May 2017 17:30:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,321,1491289200"; d="scan'208";a="855369642" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by FMSMGA003.fm.intel.com with ESMTP; 10 May 2017 17:30:40 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 10 May 2017 17:30:39 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.117]) by shsmsx102.ccr.corp.intel.com ([169.254.2.246]) with mapi id 14.03.0319.002; Thu, 11 May 2017 08:30:36 +0800 From: "Fan, Jeff" To: Brijesh Singh , "edk2-devel@lists.01.org" CC: "Thomas.Lendacky@amd.com" , "leo.duran@amd.com" , "Justen, Jordan L" , "Laszlo Ersek" , "Gao, Liming" Thread-Topic: [RFC v4 01/13] UefiCpuPkg: Define AMD Memory Encryption specific CPUID and MSR Thread-Index: AQHSydojc+E2nFGBAEqkchXhoUPhqaHuR6eQ Date: Thu, 11 May 2017 00:30:36 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C5CE28A@SHSMSX103.ccr.corp.intel.com> References: <1494454162-9940-1-git-send-email-brijesh.singh@amd.com> <1494454162-9940-2-git-send-email-brijesh.singh@amd.com> In-Reply-To: <1494454162-9940-2-git-send-email-brijesh.singh@amd.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYzFlNTg5YjktZDUwOS00ZjE1LWFiMWItMWE0NDFmMWJhZTQ0IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IkNjZm4zbzhVbXpQS3JxVXBkeFB2U0ZWVWNSK2hrZnh2bGtyb0ZMWkU3Q3c9In0= x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [RFC v4 01/13] UefiCpuPkg: Define AMD Memory Encryption specific CPUID and MSR X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 11 May 2017 00:30:41 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jeff Fan -----Original Message----- From: Brijesh Singh [mailto:brijesh.singh@amd.com]=20 Sent: Thursday, May 11, 2017 6:09 AM To: edk2-devel@lists.01.org Cc: Thomas.Lendacky@amd.com; leo.duran@amd.com; Brijesh Singh; Justen, Jord= an L; Laszlo Ersek; Fan, Jeff; Gao, Liming Subject: [RFC v4 01/13] UefiCpuPkg: Define AMD Memory Encryption specific C= PUID and MSR The patch defines AMD's Memory Encryption Information CPUID leaf and SEV st= atus MSR. The complete description for CPUID leaf is available in APM volum= e 2, Section 15.34. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Jeff Fan Cc: Liming Gao Cc: Leo Duran Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brijesh Singh --- UefiCpuPkg/Include/Register/Amd/Cpuid.h | 162 ++++++++++++++++++++ UefiCpuPkg/Include/Register/Amd/Fam17Msr.h | 62 ++++++++ UefiCpuPkg/Include/Register/Amd/Msr.h | 29 ++++ 3 files changed, 253 insertions(+) diff --git a/UefiCpuPkg/Include/Register/Amd/Cpuid.h b/UefiCpuPkg/Include/R= egister/Amd/Cpuid.h new file mode 100644 index 000000000000..5cd42667dc46 --- /dev/null +++ b/UefiCpuPkg/Include/Register/Amd/Cpuid.h @@ -0,0 +1,162 @@ +/** @file + CPUID leaf definitions. + + Provides defines for CPUID leaf indexes. Data structures are=20 + provided for registers returned by a CPUID leaf that contain one or more= bit fields. + If a register returned is a single 32-bit value, then a data=20 + structure is not provided for that register. + + Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
=20 + This program and the accompanying materials are licensed and made=20 + available under the terms and conditions of the BSD License which=20 + accompanies this distribution. The full text of the license may be=20 + found at http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, =20 + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + + @par Specification Reference: + AMD64 Architecture Programming Manaul volume 2, March 2017, Sections=20 + 15.34 + +**/ + +#ifndef __AMD_CPUID_H__ +#define __AMD_CPUID_H__ + +/** + + Memory Encryption Information + + @param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F) + + @retval EAX Returns the memory encryption feature support status. + @retval EBX If memory encryption feature is present then return + the page table bit number used to enable memory encryption= support + and reducing of physical address space in bits. + @retval ECX Returns number of encrypted guest supported simultaneosuly= . + @retval EDX Returns minimum SEV enabled and SEV disbled ASID.. + + Example usage + @code + UINT32 Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; + + AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx); + @endcode +**/ + +#define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F + +/** + CPUID Memory Encryption support information EAX for CPUID leaf + #CPUID_MEMORY_ENCRYPTION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Secure Memory Encryption (Sme) Support + /// + UINT32 SmeBit:1; + + /// + /// [Bit 1] Secure Encrypted Virtualization (Sev) Support + /// + UINT32 SevBit:1; + + /// + /// [Bit 2] Page flush MSR support + /// + UINT32 PageFlushMsrBit:1; + + /// + /// [Bit 3] Encrypted state support + /// + UINT32 SevEsBit:1; + + /// + /// [Bit 4:31] Reserved + /// + UINT32 ReservedBits:28; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MEMORY_ENCRYPTION_INFO_EAX; + +/** + CPUID Memory Encryption support information EBX for CPUID leaf + #CPUID_MEMORY_ENCRYPTION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0:5] Page table bit number used to enable memory encryption + /// + UINT32 PtePosBits:6; + + /// + /// [Bit 6:11] Reduction of system physical address space bits when me= mory encryption is enabled + /// + UINT32 ReducedPhysBits:5; + + /// + /// [Bit 12:31] Reserved + /// + UINT32 ReservedBits:21; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MEMORY_ENCRYPTION_INFO_EBX; + +/** + CPUID Memory Encryption support information ECX for CPUID leaf + #CPUID_MEMORY_ENCRYPTION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0:31] Number of encrypted guest supported simultaneously + /// + UINT32 NumGuests; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MEMORY_ENCRYPTION_INFO_ECX; + +/** + CPUID Memory Encryption support information EDX for CPUID leaf + #CPUID_MEMORY_ENCRYPTION_INFO. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0:31] Minimum SEV enabled, SEV-ES disabled ASID + /// + UINT32 MinAsid; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_MEMORY_ENCRYPTION_INFO_EDX; + +#endif diff --git a/UefiCpuPkg/Include/Register/Amd/Fam17Msr.h b/UefiCpuPkg/Includ= e/Register/Amd/Fam17Msr.h new file mode 100644 index 000000000000..2c5d9738fae8 --- /dev/null +++ b/UefiCpuPkg/Include/Register/Amd/Fam17Msr.h @@ -0,0 +1,62 @@ +/** @file + MSR Definitions. + + Provides defines for Machine Specific Registers(MSR) indexes. Data=20 + structures are provided for MSRs that contain one or more bit fields. =20 + If the MSR value returned is a single 32-bit or 64-bit value, then a=20 + data structure is not provided for that MSR. + + Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
=20 + This program and the accompanying materials are licensed and made=20 + available under the terms and conditions of the BSD License which=20 + accompanies this distribution. The full text of the license may be=20 + found at http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, =20 + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + + @par Specification Reference: + AMD64 Architecture Programming Manaul volume 2, March 2017, Sections=20 + 15.34 + +**/ + +#ifndef __FAM17_MSR_H +#define __FAM17_MSR_H + +/** + Secure Encrypted Virtualization (SEV) status register + +**/ +#define MSR_SEV_STATUS 0xc0010131 + +/** + MSR information returned for #MSR_SEV_STATUS **/ typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled + /// + UINT32 SevBit:1; + + /// + /// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is= enabled + /// + UINT32 SevEsBit:1; + + UINT32 Reserved:30; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_SEV_STATUS_REGISTER; + +#endif diff --git a/UefiCpuPkg/Include/Register/Amd/Msr.h b/UefiCpuPkg/Include/Reg= ister/Amd/Msr.h new file mode 100644 index 000000000000..bde830feb0c5 --- /dev/null +++ b/UefiCpuPkg/Include/Register/Amd/Msr.h @@ -0,0 +1,29 @@ +/** @file + MSR Definitions. + + Provides defines for Machine Specific Registers(MSR) indexes. Data=20 + structures are provided for MSRs that contain one or more bit fields. =20 + If the MSR value returned is a single 32-bit or 64-bit value, then a=20 + data structure is not provided for that MSR. + + Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
=20 + This program and the accompanying materials are licensed and made=20 + available under the terms and conditions of the BSD License which=20 + accompanies this distribution. The full text of the license may be=20 + found at http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, =20 + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + + @par Specification Reference: + AMD64 Architecture Programming Manaul volume 2, March 2017, Sections=20 + 15.34 + +**/ + +#ifndef __AMD_MSR_H__ +#define __AMD_MSR_H__ + +#include +#include + +#endif -- 2.7.4