From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F02A32095A1D5 for ; Thu, 18 May 2017 18:27:56 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP; 18 May 2017 18:27:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,361,1491289200"; d="scan'208";a="89320844" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga004.jf.intel.com with ESMTP; 18 May 2017 18:27:56 -0700 Received: from fmsmsx113.amr.corp.intel.com (10.18.116.7) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 18 May 2017 18:27:56 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by FMSMSX113.amr.corp.intel.com (10.18.116.7) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 18 May 2017 18:27:55 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.246]) by SHSMSX104.ccr.corp.intel.com ([10.239.4.70]) with mapi id 14.03.0319.002; Fri, 19 May 2017 09:27:53 +0800 From: "Fan, Jeff" To: "Kinney, Michael D" , "edk2-devel@lists.01.org" CC: Andrew Fish , Laszlo Ersek Thread-Topic: [Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add missing JMP instruction Thread-Index: AQHS0AKbKnZKIhktZ0eq6DpJfCKFX6H63iEA Date: Fri, 19 May 2017 01:27:53 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C5E4A64@shsmsx102.ccr.corp.intel.com> References: <1495131268-25444-1-git-send-email-michael.d.kinney@intel.com> In-Reply-To: <1495131268-25444-1-git-send-email-michael.d.kinney@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNjA2YWQxNDQtMzI5MS00OTY4LWEwNDktNjdiODVmZGE3OGVlIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6ImEyV0NFMHFvOFdudVwvZ3RjTFMxV2hSV1NDRlZmMHRubGowOE4zSTVQcnlFPSJ9 x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add missing JMP instruction X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 19 May 2017 01:27:57 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jeff Fan -----Original Message----- From: Kinney, Michael D=20 Sent: Friday, May 19, 2017 2:14 AM To: edk2-devel@lists.01.org Cc: Fan, Jeff; Andrew Fish; Laszlo Ersek Subject: [Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add missing JMP instruction https://bugzilla.tianocore.org/show_bug.cgi?id=3D555 Add JMP instruction in SmiEntry.S file that is missing. This updates SmiEn= try.S to match the logic in SmiEntry.asm and SmiEntry.nasm. The default BUILDRULEORDER has .nasm higher priority than .asm or .S, so th= is issue was not seen with MSFT or GCC tool chain families. The XCODE5 too= l chain overrides the BUILDRULEORDER with .S higher than .nasm, so this iss= ue was only seen when using XCODE5 tool chain when IA32 SMM is enabled. Cc: Jeff Fan Cc: Andrew Fish Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney --- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S b/UefiCpuPkg/PiSmmCp= uDxeSmm/Ia32/SmiEntry.S index 62f1697..3243a91 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S @@ -1,6 +1,6 @@ #-------------------------------------------------------------------------= ----- # -# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2009 - 2017, Intel Corporation. All rights=20 +reserved.
# This program and the accompanying materials # are licensed and made ava= ilable under the terms and conditions of the BSD License # which accompani= es this distribution. The full text of the license may be found at @@ -159= ,6 +159,7 @@ L13: rdmsr orw $MSR_EFER_XD,%ax # enable NXE wrmsr + jmp NxeDone SkipNxe: subl $4, %esp NxeDone: -- 2.6.3.windows.1