[Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add missing JMP instruction

[Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add missing JMP instruction

[Michael Kinney]

https://bugzilla.tianocore.org/show_bug.cgi?id=555

Add JMP instruction in SmiEntry.S file that is missing.  This
updates SmiEntry.S to match the logic in SmiEntry.asm and
SmiEntry.nasm.

The default BUILDRULEORDER has .nasm higher priority than
.asm or .S, so this issue was not seen with MSFT or GCC
tool chain families.  The XCODE5 tool chain overrides the
BUILDRULEORDER with .S higher than .nasm, so this issue
was only seen when using XCODE5 tool chain when IA32 SMM
is enabled.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
---
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
index 62f1697..3243a91 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
@@ -1,6 +1,6 @@
 #------------------------------------------------------------------------------
 #
-# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
 # This program and the accompanying materials
 # are licensed and made available under the terms and conditions of the BSD License
 # which accompanies this distribution.  The full text of the license may be found at
@@ -159,6 +159,7 @@ L13:
     rdmsr
     orw     $MSR_EFER_XD,%ax               # enable NXE
     wrmsr
+    jmp     NxeDone
 SkipNxe:
     subl    $4, %esp
 NxeDone:
-- 
2.6.3.windows.1

Re: [Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add missing JMP instruction

[Laszlo Ersek]

On 05/18/17 20:14, Michael Kinney wrote:
> https://bugzilla.tianocore.org/show_bug.cgi?id=555
> 
> Add JMP instruction in SmiEntry.S file that is missing.  This
> updates SmiEntry.S to match the logic in SmiEntry.asm and
> SmiEntry.nasm.
> 
> The default BUILDRULEORDER has .nasm higher priority than
> .asm or .S, so this issue was not seen with MSFT or GCC
> tool chain families.  The XCODE5 tool chain overrides the
> BUILDRULEORDER with .S higher than .nasm, so this issue
> was only seen when using XCODE5 tool chain when IA32 SMM
> is enabled.
> 
> Cc: Jeff Fan <jeff.fan@intel.com>
> Cc: Andrew Fish <afish@apple.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
> ---
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
> index 62f1697..3243a91 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
> @@ -1,6 +1,6 @@
>  #------------------------------------------------------------------------------
>  #
> -# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
>  # This program and the accompanying materials
>  # are licensed and made available under the terms and conditions of the BSD License
>  # which accompanies this distribution.  The full text of the license may be found at
> @@ -159,6 +159,7 @@ L13:
>      rdmsr
>      orw     $MSR_EFER_XD,%ax               # enable NXE
>      wrmsr
> +    jmp     NxeDone
>  SkipNxe:
>      subl    $4, %esp
>  NxeDone:
> 

Reviewed-by: Laszlo Ersek <lersek@redhat.com>

Re: [Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add missing JMP instruction

[Fan, Jeff]

Reviewed-by: Jeff Fan <jeff.fan@intel.com>

-----Original Message-----
From: Kinney, Michael D 
Sent: Friday, May 19, 2017 2:14 AM
To: edk2-devel@lists.01.org
Cc: Fan, Jeff; Andrew Fish; Laszlo Ersek
Subject: [Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add missing JMP instruction

https://bugzilla.tianocore.org/show_bug.cgi?id=555

Add JMP instruction in SmiEntry.S file that is missing.  This updates SmiEntry.S to match the logic in SmiEntry.asm and SmiEntry.nasm.

The default BUILDRULEORDER has .nasm higher priority than .asm or .S, so this issue was not seen with MSFT or GCC tool chain families.  The XCODE5 tool chain overrides the BUILDRULEORDER with .S higher than .nasm, so this issue was only seen when using XCODE5 tool chain when IA32 SMM is enabled.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
---
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
index 62f1697..3243a91 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
@@ -1,6 +1,6 @@
 #------------------------------------------------------------------------------
 #
-# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2009 - 2017, Intel Corporation. All rights 
+reserved.<BR>
 # This program and the accompanying materials  # are licensed and made available under the terms and conditions of the BSD License  # which accompanies this distribution.  The full text of the license may be found at @@ -159,6 +159,7 @@ L13:
     rdmsr
     orw     $MSR_EFER_XD,%ax               # enable NXE
     wrmsr
+    jmp     NxeDone
 SkipNxe:
     subl    $4, %esp
 NxeDone:
--
2.6.3.windows.1