From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 29A9E21A6F108 for ; Thu, 18 May 2017 18:32:20 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 May 2017 18:32:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,361,1491289200"; d="scan'208";a="89322123" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga004.jf.intel.com with ESMTP; 18 May 2017 18:32:19 -0700 Received: from fmsmsx115.amr.corp.intel.com (10.18.116.19) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 18 May 2017 18:32:19 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by fmsmsx115.amr.corp.intel.com (10.18.116.19) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 18 May 2017 18:32:19 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.246]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.117]) with mapi id 14.03.0319.002; Fri, 19 May 2017 09:32:17 +0800 From: "Fan, Jeff" To: "Kinney, Michael D" , "edk2-devel@lists.01.org" CC: Andrew Fish Thread-Topic: [Patch] UefiCpuPkg/BaseUefiCpuLib: Use NASM read-only data section name Thread-Index: AQHS0AbD8dhHntNWmkWn3ijLFn0DKKH6321w Date: Fri, 19 May 2017 01:32:17 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C5E4A99@shsmsx102.ccr.corp.intel.com> References: <1495133054-25868-1-git-send-email-michael.d.kinney@intel.com> In-Reply-To: <1495133054-25868-1-git-send-email-michael.d.kinney@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYmI3ZTk3YTctYTkyZC00MjJjLWEzZGUtY2MyNTZiOThkNDg0IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6Im5iMkNFM0hUeFVRbDVuVVdQZXNGVUNPVDlUc3NNRUZcL3JNdUlJQW53akY0PSJ9 x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch] UefiCpuPkg/BaseUefiCpuLib: Use NASM read-only data section name X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 19 May 2017 01:32:20 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jeff Fan -----Original Message----- From: Kinney, Michael D=20 Sent: Friday, May 19, 2017 2:44 AM To: edk2-devel@lists.01.org Cc: Fan, Jeff; Andrew Fish Subject: [Patch] UefiCpuPkg/BaseUefiCpuLib: Use NASM read-only data section= name https://bugzilla.tianocore.org/show_bug.cgi?id=3D556 NASM requires read-only data sections to use the section name .rodata. Thi= s fix changes .rdata to .rodata. The build failure from use of .rdata is seen when using the XCODE5 tool cha= in. Section "7.8.1 macho extensions to the SECTION Directive" of the NASM documentation at http://www.nasm.us/doc/ describes the section = name requirements. Cc: Jeff Fan Cc: Andrew Fish Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney --- UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.nasm | 4 ++-- UefiCp= uPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.nasm | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.nasm b/Ue= fiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.nasm index 55085e0..6dac4cc 100644 --- a/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.nasm +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.nasm @@ -1,6 +1,6 @@ ;-------------------------------------------------------------------------= ----- ;* -;* Copyright (c) 2016, Intel Corporation. All rights reserved.
+;* Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved. ;* This program and the accompanying materials ;* are licensed and made available under the terms and conditions of the= BSD License ;* which accompanies this distribution. The full text of the license ma= y be found at @@ -12,7 +12,7 @@ ;* ;-------------------------------------------------------------------------= ----- =20 - SECTION .rdata + SECTION .rodata =20 ; ; Float control word initial value: diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.nasm b/Uef= iCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.nasm index 904b64e..404c199 100644 --- a/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.nasm +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/X64/InitializeFpu.nasm @@ -1,6 +1,6 @@ ;-------------------------------------------------------------------------= ----- ;* -;* Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved. +;* Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved. ;* This program and the accompanying materials ;* are licensed and made available under the terms and conditions of the= BSD License ;* which accompanies this distribution. The full text of the license ma= y be found at @@ -12,7 +12,7 @@ ;* ;-------------------------------------------------------------------------= ----- =20 - SECTION .rdata + SECTION .rodata ; ; Float control word initial value: ; all exceptions masked, double-extended-precision, round-to-nearest -- 2.6.3.windows.1