From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 24B6821A16EF9 for ; Mon, 22 May 2017 19:08:33 -0700 (PDT) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 May 2017 19:08:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,379,1491289200"; d="scan'208";a="105696023" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga006.fm.intel.com with ESMTP; 22 May 2017 19:08:32 -0700 Received: from fmsmsx120.amr.corp.intel.com (10.18.124.208) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 22 May 2017 19:08:32 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx120.amr.corp.intel.com (10.18.124.208) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 22 May 2017 19:08:32 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.246]) by SHSMSX104.ccr.corp.intel.com ([10.239.4.70]) with mapi id 14.03.0319.002; Tue, 23 May 2017 10:08:30 +0800 From: "Fan, Jeff" To: "Kinney, Michael D" , "edk2-devel@lists.01.org" CC: Andrew Fish Thread-Topic: [Patch V2] UefiCpuPkg/MpInitLib: Fix X64 XCODE5/NASM compatibility issues Thread-Index: AQHS0x6fGDsIxdqslUCxOdlYEe2zgaIBK4ew Date: Tue, 23 May 2017 02:08:28 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C5E8084@shsmsx102.ccr.corp.intel.com> References: <1495473154-18184-1-git-send-email-michael.d.kinney@intel.com> In-Reply-To: <1495473154-18184-1-git-send-email-michael.d.kinney@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNDUxZTIxMWItYmM3NC00YTYyLThkOTktYjRkNzdlZDc3MDRkIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IlFCSjdpYjU0TXpXeUJtXC9JSjBqSWhjOXBNQmh3dGlEVWlSTngrWExuaTdnPSJ9 x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch V2] UefiCpuPkg/MpInitLib: Fix X64 XCODE5/NASM compatibility issues X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 23 May 2017 02:08:33 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jeff Fan -----Original Message----- From: Kinney, Michael D=20 Sent: Tuesday, May 23, 2017 1:13 AM To: edk2-devel@lists.01.org Cc: Andrew Fish; Fan, Jeff; Kinney, Michael D Subject: [Patch V2] UefiCpuPkg/MpInitLib: Fix X64 XCODE5/NASM compatibility= issues https://bugzilla.tianocore.org/show_bug.cgi?id=3D565 Fix NASM compatibility issues with XCODE5 tool chain. The XCODE5 tool chain for X64 builds using PIE (Position Independent Execut= able). For most assembly sources using PIE mode does not cause any issues. However, if assembly code is copied to a different address (such as AP star= tup code in the MpInitLib), then the X64 assembly source must be implemented to be compatible with PIE mode that= uses RIP relative addressing. The specific changes in this patch are: * Use LEA instruction instead of MOV instruction to lookup the addresses of functions. * The assembly function RendezvousFunnelProc() is copied below 1MB so it can be executed as part of the MpInitLib AP startup sequence. RendezvousFunnelProc() calls the external function InitializeFloatingPointUnits(). The absolute address of InitializeFloatingPointUnits() is added to the MP_CPU_EXCHANGE_INFO structure that is passed to RendezvousFunnelProc(). Cc: Andrew Fish Cc: Jeff Fan Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael D Kinney --- UefiCpuPkg/Library/MpInitLib/MpLib.c | 2 ++ UefiCpuPkg/Library/MpInitLib/MpLib.h | 1 + UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc | 1 + UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 8 ++++---- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index 407c44c..735e099 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -751,6 +751,8 @@ FillExchangeInfoData ( =20 ExchangeInfo->EnableExecuteDisable =3D IsBspExecuteDisableEnabled (); =20 + ExchangeInfo->InitializeFloatingPointUnitsAddress =3D=20 + (UINTN)InitializeFloatingPointUnits; + // // Get the BSP's data of GDT and IDT // diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 989b3f8..ea56412 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -177,6 +177,7 @@ typedef struct { UINTN InitFlag; CPU_INFO_IN_HOB *CpuInfo; CPU_MP_DATA *CpuMpData; + UINTN InitializeFloatingPointUnitsAddress; } MP_CPU_EXCHANGE_INFO; =20 #pragma pack() diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc b/UefiCpuPkg/Librar= y/MpInitLib/X64/MpEqu.inc index a63cd23..852281a 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc @@ -40,4 +40,5 @@ EnableExecuteDisableLocation equ LockLocation + 5= Ch Cr3Location equ LockLocation + 64h InitFlagLocation equ LockLocation + 6Ch CpuInfoLocation equ LockLocation + 74h +InitializeFloatingPointUnitsAddress equ LockLocation + 84h =20 diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Lib= rary/MpInitLib/X64/MpFuncs.nasm index fa54d01..0b14a53 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserve= d.
+; Copyright (c) 2015 - 2017, Intel Corporation. All rights=20 +reserved.
; This program and the accompanying materials ; are licensed and made ava= ilable under the terms and conditions of the BSD License ; which accompani= es this distribution. The full text of the license may be found at @@ -201= ,7 +201,7 @@ CProcedureInvoke: push rbp mov rbp, rsp =20 - mov rax, ASM_PFX(InitializeFloatingPointUnits) + mov rax, qword [esi + InitializeFloatingPointUnitsAddress] sub rsp, 20h call rax ; Call assembly function to initialize FP= U per UEFI spec add rsp, 20h @@ -282,11 +282,11 @@ AsmRelocateApLoopEnd: ;-------------------------------------------------------------------------= ------------ global ASM_PFX(AsmGetAddressMap) ASM_PFX(AsmGetAddressMap): - mov rax, ASM_PFX(RendezvousFunnelProc) + lea rax, [ASM_PFX(RendezvousFunnelProc)] mov qword [rcx], rax mov qword [rcx + 8h], LongModeStart - RendezvousFunnelProcStar= t mov qword [rcx + 10h], RendezvousFunnelProcEnd - RendezvousFunn= elProcStart - mov rax, ASM_PFX(AsmRelocateApLoop) + lea rax, [ASM_PFX(AsmRelocateApLoop)] mov qword [rcx + 18h], rax mov qword [rcx + 20h], AsmRelocateApLoopEnd - AsmRelocateApLoop= Start ret -- 2.6.3.windows.1