From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A201D21A00ACB for ; Wed, 28 Jun 2017 18:51:18 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Jun 2017 18:52:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,278,1496127600"; d="scan'208";a="104906725" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga002.jf.intel.com with ESMTP; 28 Jun 2017 18:52:47 -0700 Received: from fmsmsx111.amr.corp.intel.com (10.18.116.5) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 28 Jun 2017 18:52:47 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx111.amr.corp.intel.com (10.18.116.5) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 28 Jun 2017 18:52:44 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.146]) by SHSMSX104.ccr.corp.intel.com ([10.239.4.70]) with mapi id 14.03.0319.002; Thu, 29 Jun 2017 09:52:42 +0800 From: "Fan, Jeff" To: "Bi, Dandan" , "edk2-devel@lists.01.org" Thread-Topic: [patch] UefiCpuPkg: Fix coding style issues Thread-Index: AQHS77hTToh6jqou9kuN3zfAFIxz+KI7FUSw Date: Thu, 29 Jun 2017 01:52:42 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C6195E2@shsmsx102.ccr.corp.intel.com> References: <1498617758-21960-1-git-send-email-dandan.bi@intel.com> In-Reply-To: <1498617758-21960-1-git-send-email-dandan.bi@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOGFkMzg1OTctOGNlYi00Njg2LTg0YmItMmFjOThkNjQ1ODAyIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6InRBZmNZSlo2TzRMdlIwSFwvOEdZdWRBVUh1aU85MTQ4dndIWGtvMXJZeENJPSJ9 x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [patch] UefiCpuPkg: Fix coding style issues X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 29 Jun 2017 01:51:18 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jeff Fan -----Original Message----- From: Bi, Dandan=20 Sent: Wednesday, June 28, 2017 10:43 AM To: edk2-devel@lists.01.org Cc: Brijesh Singh; Fan, Jeff Subject: [patch] UefiCpuPkg: Fix coding style issues Cc: Brijesh Singh Cc: Jeff Fan Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi --- UefiCpuPkg/Include/Register/Amd/Fam17Msr.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Include/Register/Amd/Fam17Msr.h b/UefiCpuPkg/Includ= e/Register/Amd/Fam17Msr.h index 2c5d973..9a79de1 100644 --- a/UefiCpuPkg/Include/Register/Amd/Fam17Msr.h +++ b/UefiCpuPkg/Include/Register/Amd/Fam17Msr.h @@ -18,12 +18,12 @@ @par Specification Reference: AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.= 34 =20 **/ =20 -#ifndef __FAM17_MSR_H -#define __FAM17_MSR_H +#ifndef __FAM17_MSR_H__ +#define __FAM17_MSR_H__ =20 /** Secure Encrypted Virtualization (SEV) status register =20 **/ --=20 1.9.5.msysgit.1