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From: "Fan, Jeff" <jeff.fan@intel.com>
To: "Zeng, Star" <star.zeng@intel.com>,
	"edk2-devel@lists.01.org" <edk2-devel@lists.01.org>
Cc: "Gao, Liming" <liming.gao@intel.com>
Subject: Re: [PATCH 1/3] UefiCpuPkg SecCore: Adjust PeiTemporaryRamBase&Size to be 8byte aligned
Date: Mon, 31 Jul 2017 04:55:22 +0000	[thread overview]
Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C631854@shsmsx102.ccr.corp.intel.com> (raw)
In-Reply-To: <1501471917-11272-2-git-send-email-star.zeng@intel.com>

Reviewed-by: Jeff Fan <jeff.fan@intel.com>

-----Original Message-----
From: Zeng, Star 
Sent: Monday, July 31, 2017 11:32 AM
To: edk2-devel@lists.01.org
Cc: Zeng, Star; Gao, Liming; Fan, Jeff
Subject: [PATCH 1/3] UefiCpuPkg SecCore: Adjust PeiTemporaryRamBase&Size to be 8byte aligned

As HOB which has 8byte aligned requirement will be built based on them in PEI phase.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
---
 UefiCpuPkg/SecCore/SecMain.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c index 077d0db49f53..a53fa04cc303 100644
--- a/UefiCpuPkg/SecCore/SecMain.c
+++ b/UefiCpuPkg/SecCore/SecMain.c
@@ -1,7 +1,7 @@
 /** @file
   C functions in SEC
 
-  Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2008 - 2017, Intel Corporation. All rights 
+ reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at @@ -230,6 +230,11 @@ SecStartupPhase2(
     ASSERT (SecCoreData->PeiTemporaryRamSize > Index * sizeof (EFI_PEI_PPI_DESCRIPTOR));
     SecCoreData->PeiTemporaryRamBase = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + Index * sizeof (EFI_PEI_PPI_DESCRIPTOR));
     SecCoreData->PeiTemporaryRamSize = SecCoreData->PeiTemporaryRamSize - Index * sizeof (EFI_PEI_PPI_DESCRIPTOR);
+    //
+    // Adjust the Base and Size to be 8-byte aligned.
+    //
+    SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07);
+    SecCoreData->PeiTemporaryRamSize &= ~0x07;
   } else {
     //
     // No addition PPI, PpiList directly point to the common PPI list.
--
2.7.0.windows.1



  reply	other threads:[~2017-07-31  4:54 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-31  3:31 [PATCH 0/3] Add SecPerformancePpiCallBack to get SEC performance data in SecCore Star Zeng
2017-07-31  3:31 ` [PATCH 1/3] UefiCpuPkg SecCore: Adjust PeiTemporaryRamBase&Size to be 8byte aligned Star Zeng
2017-07-31  4:55   ` Fan, Jeff [this message]
2017-07-31  3:31 ` [PATCH 2/3] UefiCpuPkg SecCore: Add SecPerformancePpiCallBack Star Zeng
2017-07-31  4:56   ` Fan, Jeff
2017-07-31  3:31 ` [PATCH 3/3] MdeModulePkg FirmwarePerfPei: Remove SEC performance data getting code Star Zeng
2017-08-01  9:01 ` [PATCH 0/3] Add SecPerformancePpiCallBack to get SEC performance data in SecCore Gao, Liming

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