From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A424221D19921 for ; Sun, 30 Jul 2017 21:54:39 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Jul 2017 21:56:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,440,1496127600"; d="scan'208";a="1178071817" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga001.fm.intel.com with ESMTP; 30 Jul 2017 21:56:44 -0700 Received: from fmsmsx111.amr.corp.intel.com (10.18.116.5) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 30 Jul 2017 21:55:25 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx111.amr.corp.intel.com (10.18.116.5) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 30 Jul 2017 21:55:24 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.146]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.122]) with mapi id 14.03.0319.002; Mon, 31 Jul 2017 12:55:23 +0800 From: "Fan, Jeff" To: "Zeng, Star" , "edk2-devel@lists.01.org" CC: "Gao, Liming" Thread-Topic: [PATCH 1/3] UefiCpuPkg SecCore: Adjust PeiTemporaryRamBase&Size to be 8byte aligned Thread-Index: AQHTCa2XB/MKCgOepEKQ/hjvVWVceaJtXvpA Date: Mon, 31 Jul 2017 04:55:22 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C631854@shsmsx102.ccr.corp.intel.com> References: <1501471917-11272-1-git-send-email-star.zeng@intel.com> <1501471917-11272-2-git-send-email-star.zeng@intel.com> In-Reply-To: <1501471917-11272-2-git-send-email-star.zeng@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZjJmMDQ2MTUtMWJhOC00NTRkLWIyYmMtMTI2NTE4YTM5M2ZmIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6Illld3IzaGM2YTRWdnkzNkdLNnhpZ3YrMGdpRFVzbW8rcDIwdXZXWWFlTDQ9In0= x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 1/3] UefiCpuPkg SecCore: Adjust PeiTemporaryRamBase&Size to be 8byte aligned X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 31 Jul 2017 04:54:39 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jeff Fan -----Original Message----- From: Zeng, Star=20 Sent: Monday, July 31, 2017 11:32 AM To: edk2-devel@lists.01.org Cc: Zeng, Star; Gao, Liming; Fan, Jeff Subject: [PATCH 1/3] UefiCpuPkg SecCore: Adjust PeiTemporaryRamBase&Size to= be 8byte aligned As HOB which has 8byte aligned requirement will be built based on them in P= EI phase. Cc: Liming Gao Cc: Jeff Fan Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng --- UefiCpuPkg/SecCore/SecMain.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c in= dex 077d0db49f53..a53fa04cc303 100644 --- a/UefiCpuPkg/SecCore/SecMain.c +++ b/UefiCpuPkg/SecCore/SecMain.c @@ -1,7 +1,7 @@ /** @file C functions in SEC =20 - Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2008 - 2017, Intel Corporation. All rights=20 + reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -230,6 +230,11 @@ SecStartupPhase2( ASSERT (SecCoreData->PeiTemporaryRamSize > Index * sizeof (EFI_PEI_PPI= _DESCRIPTOR)); SecCoreData->PeiTemporaryRamBase =3D (VOID *)((UINTN) SecCoreData->Pei= TemporaryRamBase + Index * sizeof (EFI_PEI_PPI_DESCRIPTOR)); SecCoreData->PeiTemporaryRamSize =3D SecCoreData->PeiTemporaryRamSize = - Index * sizeof (EFI_PEI_PPI_DESCRIPTOR); + // + // Adjust the Base and Size to be 8-byte aligned. + // + SecCoreData->PeiTemporaryRamBase =3D (VOID *)(((UINTN)SecCoreData->Pei= TemporaryRamBase + 7) & ~0x07); + SecCoreData->PeiTemporaryRamSize &=3D ~0x07; } else { // // No addition PPI, PpiList directly point to the common PPI list. -- 2.7.0.windows.1