From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8B00521CF951D for ; Mon, 31 Jul 2017 02:27:18 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Jul 2017 02:29:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,441,1496127600"; d="scan'208";a="884595920" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by FMSMGA003.fm.intel.com with ESMTP; 31 Jul 2017 02:29:10 -0700 Received: from FMSMSX110.amr.corp.intel.com (10.18.116.10) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 31 Jul 2017 02:29:09 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx110.amr.corp.intel.com (10.18.116.10) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 31 Jul 2017 02:29:09 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.146]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.122]) with mapi id 14.03.0319.002; Mon, 31 Jul 2017 17:29:07 +0800 From: "Fan, Jeff" To: "Fan, Jeff" , "Dong, Eric" , "edk2-devel@lists.01.org" CC: "Ni, Ruiyu" Thread-Topic: [Patch 3/3] UefiCpuPkg: Enable Processor Trace feature. Thread-Index: AQHTAF4w/IoXlFmIwkmilLWbaKBtCqJtvNQQgAAA/iA= Date: Mon, 31 Jul 2017 09:29:07 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C632DF3@shsmsx102.ccr.corp.intel.com> References: <1500448221-6264-1-git-send-email-eric.dong@intel.com> <1500448221-6264-4-git-send-email-eric.dong@intel.com> <542CF652F8836A4AB8DBFAAD40ED192A4C632DC6@shsmsx102.ccr.corp.intel.com> In-Reply-To: <542CF652F8836A4AB8DBFAAD40ED192A4C632DC6@shsmsx102.ccr.corp.intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZDlmZmJiZWMtMDRmNC00YzRkLWE3MzMtOGI5ZWI4NDFiMDFkIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6IkdLdFREdVwvanJhckZyZll1R2djczFHTmkyYTJDWmhoR0RxamkxMTZXbjNJPSJ9 x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch 3/3] UefiCpuPkg: Enable Processor Trace feature. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 31 Jul 2017 09:27:18 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Eric, Please correct the following comments. " Enhanced Intel SpeedStep" should b= e " Intel Processor Trace ". + @retval TRUE Enhanced Intel SpeedStep feature is supported. + @retval FALSE Enhanced Intel SpeedStep feature is not supported. Jeff -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Fan,= Jeff Sent: Monday, July 31, 2017 5:27 PM To: Dong, Eric; edk2-devel@lists.01.org Cc: Ni, Ruiyu Subject: Re: [edk2] [Patch 3/3] UefiCpuPkg: Enable Processor Trace feature. Eric, ProcTraceGetConfigData() is invoked by BSP only. Instead, ProcTraceSupport(= ) will be invoked by BSP/Aps. Please move CPUID check on Proc Trace capability to ProcTraceSupport(). Thanks! Jeff -----Original Message----- From: Dong, Eric Sent: Wednesday, July 19, 2017 3:10 PM To: edk2-devel@lists.01.org Cc: Fan, Jeff; Ni, Ruiyu Subject: [Patch 3/3] UefiCpuPkg: Enable Processor Trace feature. Cc: Jeff Fan Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 66 +++ .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c | 11 + .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf | 4 +- .../Library/CpuCommonFeaturesLib/ProcTrace.c | 458 +++++++++++++++++= ++++ 4 files changed, 538 insertions(+), 1 deletion(-) create mode 100644 Uefi= CpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h b/= UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h index c03e5ab..74b24f6 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h @@ -909,4 +909,70 @@ PpinInitialize ( IN BOOLEAN State ); =20 +/** + Prepares for the data used by CPU feature detection and initialization. + + @param[in] NumberOfProcessors The number of CPUs in the platform. + + @return Pointer to a buffer of CPU related configuration data. + + @note This service could be called by BSP only. +**/ +VOID * +EFIAPI +ProcTraceGetConfigData ( + IN UINTN NumberOfProcessors + ); + +/** + Detects if Intel Processor Trace feature supported on current processor. + + @param[in] ProcessorNumber The index of the CPU executing this functio= n. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFOR= MATION + structure for the CPU executing this functi= on. + @param[in] ConfigData A pointer to the configuration buffer retur= ned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provide= d in + RegisterCpuFeature(). + + @retval TRUE Enhanced Intel SpeedStep feature is supported. + @retval FALSE Enhanced Intel SpeedStep feature is not supported. + + @note This service could be called by BSP/APs. +**/ +BOOLEAN +EFIAPI +ProcTraceSupport ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData OPTIONAL + ); + +/** + Initializes Intel Processor Trace feature to specific state. + + @param[in] ProcessorNumber The index of the CPU executing this functio= n. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFOR= MATION + structure for the CPU executing this functi= on. + @param[in] ConfigData A pointer to the configuration buffer retur= ned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provide= d in + RegisterCpuFeature(). + @param[in] State If TRUE, then the Protected Processor Inven= tory=20 + Number feature must be enabled. + If FALSE, then the Protected Processor Inve= ntory=20 + Number feature must be disabled. + + @retval RETURN_SUCCESS Intel Processor Trace feature feature is in= itialized. + +**/ +RETURN_STATUS +EFIAPI +ProcTraceInitialize ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData, OPTIONAL + IN BOOLEAN State + ); + #endif diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c= b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c index b88b7d1..a4cb260 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c @@ -217,6 +217,17 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_PROC_TRACE)) { + Status =3D RegisterCpuFeature ( + "Proc Trace", + ProcTraceGetConfigData, + ProcTraceSupport, + ProcTraceInitialize, + CPU_FEATURE_PROC_TRACE, + CPU_FEATURE_END + ); + ASSERT_EFI_ERROR (Status); + } =20 return RETURN_SUCCESS; } diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.i= nf b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf index 202d560..e9225bb 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf @@ -48,6 +48,7 @@ PendingBreak.c X2Apic.c Ppin.c + ProcTrace.c =20 [Packages] MdePkg/MdePkg.dec @@ -66,4 +67,5 @@ gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport ## CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle ## SOMETIMES_= CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset ## SOMETIMES_= CONSUMES - + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme ## SOMETIMES_= CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize ## SOMETIMES_= CONSUMES \ No newline at end of file diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c b/UefiCpuP= kg/Library/CpuCommonFeaturesLib/ProcTrace.c new file mode 100644 index 0000000..e1b7579 --- /dev/null +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c @@ -0,0 +1,458 @@ +/** @file + Intel Processor Trace feature. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
This=20 + program and the accompanying materials are licensed and made=20 + available under the terms and conditions of the BSD License which=20 + accompanies this distribution. The full text of the license may be=20 + found at http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,=20 + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + +**/ + +#include "CpuCommonFeatures.h" + +#define MAX_TOPA_ENTRY_COUNT 2 + +/// +/// Processor trace buffer size selection. +/// +typedef enum { + Enum4K =3D 0, + Enum8K, + Enum16K, + Enum32K, + Enum64K, + Enum128K, + Enum256K, + Enum512K, + Enum1M, + Enum2M, + Enum4M, + Enum8M, + Enum16M, + Enum32M, + Enum64M, + Enum128M, + EnumProcTraceMemDisable +} PROC_TRACE_MEM_SIZE; + +/// +/// Processor trace output scheme selection. +/// +typedef enum { + OutputSchemeSingleRange =3D 0, + OutputSchemeToPA, + OutputSchemeInvalid +} PROC_TRACE_OUTPUT_SCHEME; + +typedef struct { + BOOLEAN ProcTraceSupported; + BOOLEAN TopaSupported; + BOOLEAN SingleRangeSupported; + UINT8 ProcTraceOutputScheme; =20 + UINT32 ProcTraceMemSize; + UINT32 NumberOfProcessors; + + UINTN *ThreadMemRegionTable; + UINTN AllocatedThreads; + + UINTN *TopaMemArray; + UINTN TopaMemArrayCount; + +} PROC_TRACE_DATA; + +typedef struct { + UINT64 TopaEntry[MAX_TOPA_ENTRY_COUNT]; +} PROC_TRACE_TOPA_TABLE; + +/** + Prepares for the data used by CPU feature detection and initialization. + + @param[in] NumberOfProcessors The number of CPUs in the platform. + + @return Pointer to a buffer of CPU related configuration data. + + @note This service could be called by BSP only. +**/ +VOID * +EFIAPI +ProcTraceGetConfigData ( + IN UINTN NumberOfProcessors + ) +{ + PROC_TRACE_DATA *ConfigData; + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx; + CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx; + + ConfigData =3D AllocateZeroPool (sizeof (PROC_TRACE_DATA)); ASSERT=20 + (ConfigData !=3D NULL); + + ConfigData->NumberOfProcessors =3D (UINT32) NumberOfProcessors; + + ConfigData->ProcTraceMemSize =3D PcdGet32 (PcdCpuProcTraceMemSize); + ConfigData->ProcTraceOutputScheme =3D PcdGet8 + (PcdCpuProcTraceOutputScheme); + + AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL,=20 + &Ebx.Uint32, NULL, NULL); ConfigData->ProcTraceSupported =3D=20 + Ebx.Bits.IntelProcessorTrace =3D=3D 1; + + if (ConfigData->ProcTraceSupported) { + AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_M= AIN_LEAF, NULL, NULL, &Ecx.Uint32, NULL); + ConfigData->TopaSupported =3D Ecx.Bits.RTIT =3D=3D 1; + ConfigData->SingleRangeSupported =3D Ecx.Bits.SingleRangeOutput =3D=3D= 1;=20 + } + + return ConfigData; +} + +/** + Detects if Intel Processor Trace feature feature supported on current + processor. + + @param[in] ProcessorNumber The index of the CPU executing this functio= n. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFOR= MATION + structure for the CPU executing this functi= on. + @param[in] ConfigData A pointer to the configuration buffer retur= ned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provide= d in + RegisterCpuFeature(). + + @retval TRUE Enhanced Intel SpeedStep feature is supported. + @retval FALSE Enhanced Intel SpeedStep feature is not supported. + + @note This service could be called by BSP/APs. +**/ +BOOLEAN +EFIAPI +ProcTraceSupport ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData OPTIONAL + ) +{ + PROC_TRACE_DATA *ProcTraceData; + + // + // Check if ProcTraceMemorySize option is enabled (0xFF means disable=20 + by user) // ProcTraceData =3D (PROC_TRACE_DATA *) ConfigData; if=20 + (ProcTraceData->ProcTraceMemSize >=3D EnumProcTraceMemDisable) { + return FALSE; + } + + // + // Check if Processor Trace is supported // if + (!ProcTraceData->ProcTraceSupported) { + return FALSE; + } + + if (ProcTraceData->TopaSupported || ProcTraceData->SingleRangeSupported)= { + return TRUE; + } + + return FALSE; +} + +/** + Initializes Intel Processor Trace feature feature to specific state. + + @param[in] ProcessorNumber The index of the CPU executing this functio= n. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFOR= MATION + structure for the CPU executing this functi= on. + @param[in] ConfigData A pointer to the configuration buffer retur= ned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provide= d in + RegisterCpuFeature(). + @param[in] State If TRUE, then the Protected Processor Inven= tory=20 + Number feature must be enabled. + If FALSE, then the Protected Processor Inve= ntory=20 + Number feature must be disabled. + + @retval RETURN_SUCCESS Intel Processor Trace feature feature is in= itialized. + +**/ +RETURN_STATUS +EFIAPI +ProcTraceInitialize ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData, OPTIONAL + IN BOOLEAN State + ) +{ + UINT64 MsrValue; + UINT32 MemRegionSize; + UINTN Pages; + UINTN Alignment; + UINTN MemRegionBaseAddr; + UINTN *ThreadMemRegionTable; + UINTN Index; + UINTN TopaTableBaseAddr; + UINTN AlignedAddress; + UINTN *TopaMemArray; + PROC_TRACE_TOPA_TABLE *TopaTable; + PROC_TRACE_DATA *ProcTraceData; + BOOLEAN IsBsp; + + ProcTraceData =3D (PROC_TRACE_DATA *) ConfigData; + + MemRegionBaseAddr =3D 0; + IsBsp =3D FALSE; + + if (ProcessorNumber =3D=3D 0) { + IsBsp =3D TRUE; + DEBUG ((DEBUG_INFO, "Initialize Processor Trace\n")); } + + /// + /// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding ///=20 + MemRegionSize =3D (UINT32) (1 << (ProcTraceData->ProcTraceMemSize +=20 + 12)); if (IsBsp) { + DEBUG ((DEBUG_INFO, "ProcTrace: MemSize requested: 0x%X \n",=20 + MemRegionSize)); } + + // + // Clear MSR_IA32_RTIT_CTL[0] and IA32_RTIT_STS only if=20 + MSR_IA32_RTIT_CTL[0]=3D=3D1b // MsrValue =3D AsmReadMsr64=20 + (MSR_IA32_RTIT_CTL); if ((MsrValue & BIT0) !=3D 0) { + /// + /// Clear bit 0 in MSR IA32_RTIT_CTL (570) + /// + MsrValue &=3D (UINT64) ~BIT0; + CPU_REGISTER_TABLE_WRITE64 ( + ProcessorNumber, + Msr, + MSR_IA32_RTIT_CTL, + MsrValue + ); + + /// + /// Clear MSR IA32_RTIT_STS (571h) to all zeros + /// + MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_STATUS); + MsrValue &=3D 0x0; + CPU_REGISTER_TABLE_WRITE64 ( + ProcessorNumber, + Msr, + MSR_IA32_RTIT_STATUS, + MsrValue + ); + } + + if (IsBsp) { + // + // Let BSP allocate and create the necessary memory region (Aligned = to the size of + // the memory region from setup option(ProcTraceMemSize) which is an= integral multiple of 4kB) + // for the all the enabled threads for storing Processor Trace debug= data. Then Configure the trace + // address base in MSR, IA32_RTIT_OUTPUT_BASE (560h) bits 47:12. Not= e that all regions must be + // aligned based on their size, not just 4K. Thus a 2M region must h= ave bits 20:12 clear. + // + ThreadMemRegionTable =3D (UINTN *) AllocatePool (ProcTraceData->Number= OfProcessors * sizeof (UINTN *)); + if (ThreadMemRegionTable =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Allocate ProcTrace ThreadMemRegionTable Failed= \n")); + return RETURN_OUT_OF_RESOURCES; + } + ProcTraceData->ThreadMemRegionTable =3D ThreadMemRegionTable; + + for (Index =3D 0; Index < ProcTraceData->NumberOfProcessors; Index++, = ProcTraceData->AllocatedThreads++) { + Pages =3D EFI_SIZE_TO_PAGES (MemRegionSize); + Alignment =3D MemRegionSize; + AlignedAddress =3D (UINTN) AllocateAlignedReservedPages (Pages, Alig= nment); + if (AlignedAddress =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated only for %d= threads\n", ProcTraceData->AllocatedThreads)); + if (Index =3D=3D 0) { + // + // Could not allocate for BSP even + // + FreePool ((VOID *) ThreadMemRegionTable); + ThreadMemRegionTable =3D NULL; + return RETURN_OUT_OF_RESOURCES; + } + break; + } + + ThreadMemRegionTable[Index] =3D AlignedAddress; + DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for th= read %d: 0x%llX \n", Index, (UINT64) ThreadMemRegionTable[Index])); + } + + DEBUG ((DEBUG_INFO, "ProcTrace: Allocated PT mem for %d thread \n", Pr= ocTraceData->AllocatedThreads)); + MemRegionBaseAddr =3D ThreadMemRegionTable[0]; } else { + if (ProcessorNumber < ProcTraceData->AllocatedThreads) { + MemRegionBaseAddr =3D ProcTraceData->ThreadMemRegionTable[ProcessorN= umber]; + } else { + return RETURN_SUCCESS; + } + } + + /// + /// Check Processor Trace output scheme: Single Range output or ToPA=20 + table /// + + // + // Single Range output scheme + // + if (ProcTraceData->SingleRangeSupported && (ProcTraceData->ProcTraceOutp= utScheme =3D=3D OutputSchemeSingleRange)) { + if (IsBsp) { + DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme = \n")); + } + + // + // Clear MSR IA32_RTIT_CTL (0x570) ToPA (Bit 8) + // + MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); + MsrValue &=3D (UINT64) ~BIT8; + CPU_REGISTER_TABLE_WRITE64 ( + ProcessorNumber, + Msr, + MSR_IA32_RTIT_CTL, + MsrValue + ); + + // + // Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[47:12] with the allo= cated Memory Region + // + MsrValue =3D (UINT64) MemRegionBaseAddr; + CPU_REGISTER_TABLE_WRITE64 ( + ProcessorNumber, + Msr, + MSR_IA32_RTIT_OUTPUT_BASE, + MsrValue + ); + + // + // Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT= _MASK_PTRS (561h) + // + MsrValue =3D (UINT64) MemRegionSize - 1; + CPU_REGISTER_TABLE_WRITE64 ( + ProcessorNumber, + Msr, + MSR_IA32_RTIT_OUTPUT_MASK_PTRS, + MsrValue + ); + + } + + // + // ToPA(Table of physical address) scheme // if=20 + (ProcTraceData->TopaSupported && (ProcTraceData->ProcTraceOutputScheme = =3D=3D OutputSchemeToPA)) { + // + // Create ToPA structure aligned at 4KB for each logical thread + // with at least 2 entries by 8 bytes size each. The first entry + // should have the trace output base address in bits 47:12, 6:9 + // for Size, bits 4,2 and 0 must be cleared. The second entry + // should have the base address of the table location in bits + // 47:12, bits 4 and 2 must be cleared and bit 0 must be set. + // + if (IsBsp) { + DEBUG ((DEBUG_INFO, "ProcTrace: Enabling ToPA scheme \n")); + // + // Let BSP allocate ToPA table mem for all threads + // + TopaMemArray =3D (UINTN *) AllocatePool (ProcTraceData->AllocatedThr= eads * sizeof (UINTN *)); + if (TopaMemArray =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "ProcTrace: Allocate mem for ToPA Failed\n"))= ; + return RETURN_OUT_OF_RESOURCES; + } + ProcTraceData->TopaMemArray =3D TopaMemArray; + + for (Index =3D 0; Index < ProcTraceData->AllocatedThreads; Index++) = { + Pages =3D EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE)); + Alignment =3D 0x1000; + AlignedAddress =3D (UINTN) AllocateAlignedReservedPages (Pages, Al= ignment); + if (AlignedAddress =3D=3D 0) { + if (Index < ProcTraceData->AllocatedThreads) { + ProcTraceData->AllocatedThreads =3D Index; + } + DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocating ToPA me= m only for %d threads\n", ProcTraceData->AllocatedThreads)); + if (Index =3D=3D 0) { + // + // Could not allocate for BSP + // + FreePool ((VOID *) TopaMemArray); + TopaMemArray =3D NULL; + return RETURN_OUT_OF_RESOURCES; + } + break; + } + + TopaMemArray[Index] =3D AlignedAddress; + DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for th= read %d is 0x%llX \n", Index, (UINT64) TopaMemArray[Index])); + } + + DEBUG ((DEBUG_INFO, "ProcTrace: Allocated ToPA mem for %d thread \n"= , ProcTraceData->AllocatedThreads)); + // + // BSP gets the first block + // + TopaTableBaseAddr =3D TopaMemArray[0]; + } else { + // + // Count for currently executing AP. + // + if (ProcessorNumber < ProcTraceData->AllocatedThreads) { + TopaTableBaseAddr =3D ProcTraceData->TopaMemArray[ProcessorNumber]= ; + } else { + return RETURN_SUCCESS; + } + } + + TopaTable =3D (PROC_TRACE_TOPA_TABLE *) TopaTableBaseAddr; + TopaTable->TopaEntry[0] =3D (UINT64) (MemRegionBaseAddr | ((ProcTraceD= ata->ProcTraceMemSize) << 6)) & ~BIT0; + TopaTable->TopaEntry[1] =3D (UINT64) TopaTableBaseAddr | BIT0; + + // + // Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[47:12] with ToPA= base + // + MsrValue =3D (UINT64) TopaTableBaseAddr; + CPU_REGISTER_TABLE_WRITE64 ( + ProcessorNumber, + Msr, + MSR_IA32_RTIT_OUTPUT_BASE, + MsrValue + ); + + // + // Set the MSR IA32_RTIT_OUTPUT_MASK (0x561) bits[63:7] to 0 + // + CPU_REGISTER_TABLE_WRITE64 ( + ProcessorNumber, + Msr, + MSR_IA32_RTIT_OUTPUT_MASK_PTRS, + 0x7F + ); + // + // Enable ToPA output scheme by enabling MSR IA32_RTIT_CTL (0x570) ToP= A (Bit 8) + // + MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); + MsrValue |=3D BIT8; + CPU_REGISTER_TABLE_WRITE64 ( + ProcessorNumber, + Msr, + MSR_IA32_RTIT_CTL, + MsrValue + ); + } + + /// + /// Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h)=20 + /// MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); MsrValue |=3D + (UINT64) BIT0 + BIT2 + BIT3 + BIT13; if (!State) { + MsrValue &=3D (UINT64) ~BIT0; + } + CPU_REGISTER_TABLE_WRITE64 ( + ProcessorNumber, + Msr, + MSR_IA32_RTIT_CTL, + MsrValue + ); + + return RETURN_SUCCESS; +} -- 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel