From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 597EF2095DB92 for ; Thu, 3 Aug 2017 07:06:53 -0700 (PDT) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Aug 2017 07:09:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,316,1498546800"; d="scan'208";a="135665122" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga006.fm.intel.com with ESMTP; 03 Aug 2017 07:09:04 -0700 Received: from fmsmsx121.amr.corp.intel.com (10.18.125.36) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 3 Aug 2017 07:09:04 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx121.amr.corp.intel.com (10.18.125.36) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 3 Aug 2017 07:09:04 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.146]) by SHSMSX104.ccr.corp.intel.com ([10.239.4.70]) with mapi id 14.03.0319.002; Thu, 3 Aug 2017 22:09:02 +0800 From: "Fan, Jeff" To: "Dong, Eric" , "edk2-devel@lists.01.org" CC: "Ni, Ruiyu" Thread-Topic: [Patch 2/3] UefiCpuPkg CpuCommonFeaturesLib: Enable LMCE feature. Thread-Index: AQHTCprzxwraMmNVN0+vHKr+qCm4/aJyrYCQ Date: Thu, 3 Aug 2017 14:09:01 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C63655C@shsmsx102.ccr.corp.intel.com> References: <1501573838-10740-1-git-send-email-eric.dong@intel.com> <1501573838-10740-3-git-send-email-eric.dong@intel.com> In-Reply-To: <1501573838-10740-3-git-send-email-eric.dong@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYWIzYjIyZWQtMmZmYy00YTg4LWE3ZjEtNDk1NjAxZWE5NWU2IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6IlRqUTEwTGlQNmhUOHo2Tm5rbDl1WXRhNHJTSEpqZ0ljNk9pb0RQaGY2Nms9In0= x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch 2/3] UefiCpuPkg CpuCommonFeaturesLib: Enable LMCE feature. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 14:06:53 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Eric, Typo: " Protected Processor Inventory Number" should be " Local machine che= ck exception "=20 + @param[in] State If TRUE, then the Protected Processor Inven= tory=20 + Number feature must be enabled. + If FALSE, then the Protected Processor Inve= ntory=20 + Number feature must be disabled. + + @retval RETURN_SUCCESS Local machine check exception feature is in= itialized. Jeff -----Original Message----- From: Dong, Eric=20 Sent: Tuesday, August 01, 2017 3:51 PM To: edk2-devel@lists.01.org Cc: Fan, Jeff; Ni, Ruiyu Subject: [Patch 2/3] UefiCpuPkg CpuCommonFeaturesLib: Enable LMCE feature. Cc: Jeff Fan Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong --- .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 56 +++++++++++++- .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c | 12 +++ .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf | 1 + UefiCpuPkg/Library/CpuCommonFeaturesLib/Lmce.c | 90 ++++++++++++++++++= ++++ 4 files changed, 157 insertions(+), 2 deletions(-) create mode 100644 Uef= iCpuPkg/Library/CpuCommonFeaturesLib/Lmce.c diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h b/= UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h index c03e5ab..67a44c6 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h @@ -866,8 +866,8 @@ FeatureControlGetConfigData ( CPU_FEATURE_GET_CONFIG_DATA was not provide= d in RegisterCpuFeature(). =20 - @retval TRUE Enhanced Intel SpeedStep feature is supported. - @retval FALSE Enhanced Intel SpeedStep feature is not supported. + @retval TRUE Protected Processor Inventory Number feature is support= ed. + @retval FALSE Protected Processor Inventory Number feature is not sup= ported. =20 @note This service could be called by BSP/APs. **/ @@ -909,4 +909,56 @@ PpinInitialize ( IN BOOLEAN State ); =20 +/** + Detects if Local machine check exception feature supported on current + processor. + + @param[in] ProcessorNumber The index of the CPU executing this functio= n. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFOR= MATION + structure for the CPU executing this functi= on. + @param[in] ConfigData A pointer to the configuration buffer retur= ned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provide= d in + RegisterCpuFeature(). + + @retval TRUE Local machine check exception feature is supported. + @retval FALSE Local machine check exception feature is not supported. + + @note This service could be called by BSP/APs. +**/ +BOOLEAN +EFIAPI +LmceSupport ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData OPTIONAL + ); + +/** + Initializes Local machine check exception feature to specific state. + + @param[in] ProcessorNumber The index of the CPU executing this functio= n. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFOR= MATION + structure for the CPU executing this functi= on. + @param[in] ConfigData A pointer to the configuration buffer retur= ned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provide= d in + RegisterCpuFeature(). + @param[in] State If TRUE, then the Protected Processor Inven= tory=20 + Number feature must be enabled. + If FALSE, then the Protected Processor Inve= ntory=20 + Number feature must be disabled. + + @retval RETURN_SUCCESS Local machine check exception feature is in= itialized. + +**/ +RETURN_STATUS +EFIAPI +LmceInitialize ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData, OPTIONAL + IN BOOLEAN State + ); + #endif diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c= b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c index b88b7d1..4c78209 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c @@ -217,6 +217,18 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_LMCE)) { + Status =3D RegisterCpuFeature ( + "LMCE", + NULL, + LmceSupport, + LmceInitialize, + CPU_FEATURE_LMCE, + CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER | CPU_FEATURE_BEF= ORE, + CPU_FEATURE_END + ); + ASSERT_EFI_ERROR (Status); + } =20 return RETURN_SUCCESS; } diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.i= nf b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf index 202d560..2cca58e 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf @@ -48,6 +48,7 @@ PendingBreak.c X2Apic.c Ppin.c + Lmce.c =20 [Packages] MdePkg/MdePkg.dec diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Lmce.c b/UefiCpuPkg/Li= brary/CpuCommonFeaturesLib/Lmce.c new file mode 100644 index 0000000..8f4fa03 --- /dev/null +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Lmce.c @@ -0,0 +1,90 @@ +/** @file + Local machine check exception feature. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
This=20 + program and the accompanying materials are licensed and made=20 + available under the terms and conditions of the BSD License which=20 + accompanies this distribution. The full text of the license may be=20 + found at http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, =20 + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + +**/ + +#include "CpuCommonFeatures.h" + +/** + Detects if Local machine check exception feature supported on current + processor. + + @param[in] ProcessorNumber The index of the CPU executing this functio= n. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFOR= MATION + structure for the CPU executing this functi= on. + @param[in] ConfigData A pointer to the configuration buffer retur= ned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provide= d in + RegisterCpuFeature(). + + @retval TRUE Local machine check exception feature is supported. + @retval FALSE Local machine check exception feature is not supported. + + @note This service could be called by BSP/APs. +**/ +BOOLEAN +EFIAPI +LmceSupport ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData OPTIONAL + ) +{ + MSR_IA32_MCG_CAP_REGISTER McgCap; + + McgCap.Uint64 =3D AsmReadMsr64 (MSR_IA32_MCG_CAP); + return (BOOLEAN) (McgCap.Bits.MCG_LMCE_P !=3D 0); } + +/** + Initializes Local machine check exception feature to specific state. + + @param[in] ProcessorNumber The index of the CPU executing this functio= n. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFOR= MATION + structure for the CPU executing this functi= on. + @param[in] ConfigData A pointer to the configuration buffer retur= ned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provide= d in + RegisterCpuFeature(). + @param[in] State If TRUE, then the Protected Processor Inven= tory=20 + Number feature must be enabled. + If FALSE, then the Protected Processor Inve= ntory=20 + Number feature must be disabled. + + @retval RETURN_SUCCESS Local machine check exception feature is in= itialized. + +**/ +RETURN_STATUS +EFIAPI +LmceInitialize ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData, OPTIONAL + IN BOOLEAN State + ) +{ + MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; + + ASSERT (ConfigData !=3D NULL); + MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; + if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { + CPU_REGISTER_TABLE_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.LmceOn, + (State) ? 1 : 0 + ); + } + return RETURN_SUCCESS; +} -- 2.7.0.windows.1