From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CAF282095DB87 for ; Thu, 3 Aug 2017 07:09:55 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Aug 2017 07:12:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,316,1498546800"; d="scan'208";a="886010336" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by FMSMGA003.fm.intel.com with ESMTP; 03 Aug 2017 07:12:07 -0700 Received: from fmsmsx151.amr.corp.intel.com (10.18.125.4) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 3 Aug 2017 07:12:07 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by FMSMSX151.amr.corp.intel.com (10.18.125.4) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 3 Aug 2017 07:12:06 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.146]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.188]) with mapi id 14.03.0319.002; Thu, 3 Aug 2017 22:12:03 +0800 From: "Fan, Jeff" To: "Dong, Eric" , "edk2-devel@lists.01.org" CC: "Ni, Ruiyu" Thread-Topic: [Patch 3/3] UefiCpuPkg PiSmmCpuDxeSmm: Check LMCE capability when wait for AP. Thread-Index: AQHTCpr1Gdg3T335okyzilEROHnYgKJyr6rg Date: Thu, 3 Aug 2017 14:12:02 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C6365A2@shsmsx102.ccr.corp.intel.com> References: <1501573838-10740-1-git-send-email-eric.dong@intel.com> <1501573838-10740-4-git-send-email-eric.dong@intel.com> In-Reply-To: <1501573838-10740-4-git-send-email-eric.dong@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNzM3MzNhNjMtMzI0Ny00YzRiLWE5NjItNTQ4NzdlMDE4NWI2IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6IjZxWWZSaVZJOThGVzBGS2ZHYjcrMEhOYmJoR0Q1YVBuN2pUN3RocGMxa0U9In0= x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch 3/3] UefiCpuPkg PiSmmCpuDxeSmm: Check LMCE capability when wait for AP. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Aug 2017 14:09:56 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jeff Fan -----Original Message----- From: Dong, Eric=20 Sent: Tuesday, August 01, 2017 3:51 PM To: edk2-devel@lists.01.org Cc: Fan, Jeff; Ni, Ruiyu Subject: [Patch 3/3] UefiCpuPkg PiSmmCpuDxeSmm: Check LMCE capability when = wait for AP. Cc: Jeff Fan Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 57 +++++++++++++++++++++++++++++++= +++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index 4ac5e8e..6b66c49 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -196,6 +196,56 @@ AllCpusInSmmWithExceptions ( return TRUE; } =20 +/** + Has OS enabled Lmce in the MSR_IA32_MCG_EXT_CTL + =20 + @retval TRUE Os enable lmce. + @retval FALSE Os not enable lmce. + +**/ +BOOLEAN +IsLmceOsEnabled ( + VOID + ) +{ + MSR_IA32_MCG_CAP_REGISTER McgCap; + MSR_IA32_FEATURE_CONTROL_REGISTER FeatureCtrl; + MSR_IA32_MCG_EXT_CTL_REGISTER McgExtCtrl; + + McgCap.Uint64 =3D AsmReadMsr64 (MSR_IA32_MCG_CAP); if=20 + (McgCap.Bits.MCG_LMCE_P =3D=3D 0) { + return FALSE; + } + + FeatureCtrl.Uint64 =3D AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL); if=20 + (FeatureCtrl.Bits.LmceOn =3D=3D 0) { + return FALSE; + } + + McgExtCtrl.Uint64 =3D AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL); + return (BOOLEAN) (McgExtCtrl.Bits.LMCE_EN =3D=3D 1); } + +/** + Return if Local machine check exception signaled.=20 + + Indicates (when set) that a local machine check exception was=20 + generated. This indicates that the current machine-check event was deliv= ered to only the logical processor. + + @retval TRUE LMCE was signaled. + @retval FALSE LMCE was not signaled. + +**/ +BOOLEAN +IsLmceSignaled ( + VOID + ) +{ + MSR_IA32_MCG_STATUS_REGISTER McgStatus; + + McgStatus.Uint64 =3D AsmReadMsr64 (MSR_IA32_MCG_STATUS); + return (BOOLEAN) (McgStatus.Bits.LMCE_S =3D=3D 1); } =20 /** Given timeout constraint, wait for all APs to arrive, and insure when th= is function returns, no AP will execute normal mode code before @@ -209,9 += 259,14 @@ SmmWaitForApArrival ( { UINT64 Timer; UINTN Index; + BOOLEAN LmceEn; + BOOLEAN LmceSignal; =20 ASSERT (*mSmmMpSyncData->Counter <=3D mNumberOfCpus); =20 + LmceEn =3D IsLmceOsEnabled (); + LmceSignal =3D IsLmceSignaled(); + // // Platform implementor should choose a timeout value appropriately: // - The timeout value should balance the SMM time constrains and the li= kelihood that delayed CPUs are excluded in the SMM run. Note @@ -227,7 +282= ,7 @@ SmmWaitForApArrival ( // Sync with APs 1st timeout // for (Timer =3D StartSyncTimer (); - !IsSyncTimerTimeout (Timer) && + !IsSyncTimerTimeout (Timer) && !(LmceEn && LmceSignal) && !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EX= CEPTION_SMI_DISABLED ); ) { CpuPause (); -- 2.7.0.windows.1