From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.101.70; helo=foss.arm.com; envelope-from=marc.zyngier@arm.com; receiver=edk2-devel@lists.01.org Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by ml01.01.org (Postfix) with ESMTP id 0C7832258AF10 for ; Mon, 12 Mar 2018 02:40:23 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DB715A78; Mon, 12 Mar 2018 02:46:43 -0700 (PDT) Received: from [10.1.207.62] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EC8273F24A; Mon, 12 Mar 2018 02:46:42 -0700 (PDT) To: Heyi Guo , edk2-devel@lists.01.org Cc: Yi Li , Leif Lindholm , Ard Biesheuvel References: <1520837611-94728-1-git-send-email-heyi.guo@linaro.org> <1520837611-94728-2-git-send-email-heyi.guo@linaro.org> From: Marc Zyngier Organization: ARM Ltd Message-ID: <54c4aab8-cc61-b4cc-6ab0-325dd42cca35@arm.com> Date: Mon, 12 Mar 2018 09:46:41 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <1520837611-94728-2-git-send-email-heyi.guo@linaro.org> Subject: Re: [PATCH 1/1] ArmPkg/TimerDxe: Add DSB for timer compare value reload X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 12 Mar 2018 09:40:24 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit On 12/03/18 06:53, Heyi Guo wrote: > Resetting timer compare register has a side effect of clearing GIC > pending status, if timer interrupt is level sensitive, so a "DSB SY" > is needed to make sure this change effect is synchronized. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Heyi Guo > Signed-off-by: Yi Li > Cc: Leif Lindholm > Cc: Ard Biesheuvel > Cc: Marc Zyngier > --- > ArmPkg/Drivers/TimerDxe/TimerDxe.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c > index 33d7c922221f..b732a2ac1b64 100644 > --- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c > +++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c > @@ -337,6 +337,7 @@ TimerInterruptHandler ( > > // Set next compare value > ArmGenericTimerSetCompareVal (CompareValue); > + ArmDataSynchronizationBarrier (); > ArmGenericTimerEnableTimer (); > } > > Which HW platform is that on? DSB on its own doesn't have any effect on inputs to the GIC, only on the synchronization at the GIC system register level (see the GICv3 architecture specification, 8.1.6). I don't believe this is required. You could stick an ISB instead to ensure that the write to the CNTVCTL_EL0 is executed, but DSB feels pretty odd, unless this is a workaround for a platform erratum. Thanks, M. -- Jazz is not dead. It just smells funny...