From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [63.128.21.124]) by mx.groups.io with SMTP id smtpd.web10.929.1605317100923690427 for ; Fri, 13 Nov 2020 17:25:01 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=M4T7VSOx; spf=pass (domain: redhat.com, ip: 63.128.21.124, mailfrom: lersek@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1605317100; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=L7Ek6UCCcUsBLhJ15LQ9LkIfvmUdiva2q7FQr6E6kg0=; b=M4T7VSOxIjQlY+suceBPp8Ug7SQtPLWhhwRPJB3RQ2OQoex+mOY5woMLdLS4uLxLJUjXYM +zQBxWHDsUE9arLwvBuw4ws3GF1Q69URdeu5CRQMck7zGpVnzshBsKF7hRC2TLqX8WiBJY uLMI++cC5wmSsfb4npwGiFiINHIPNJU= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-250-wcsrCappNBKrnFDduOVu0A-1; Fri, 13 Nov 2020 20:24:57 -0500 X-MC-Unique: wcsrCappNBKrnFDduOVu0A-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id BD5C41868401; Sat, 14 Nov 2020 01:24:55 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-112-113.ams2.redhat.com [10.36.112.113]) by smtp.corp.redhat.com (Postfix) with ESMTP id 259D15B4B2; Sat, 14 Nov 2020 01:24:53 +0000 (UTC) Subject: Re: [edk2-devel] [PATCH v7 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reflect page table depth with page table address To: devel@edk2.groups.io, w.sheng@intel.com Cc: Eric Dong , Ray Ni , Rahul Kumar , Jiewen Yao References: <20201113025037.14192-1-w.sheng@intel.com> <20201113025037.14192-3-w.sheng@intel.com> From: "Laszlo Ersek" Message-ID: <56e70081-278d-c9c8-90da-57c01dafa81e@redhat.com> Date: Sat, 14 Nov 2020 02:24:53 +0100 MIME-Version: 1.0 In-Reply-To: <20201113025037.14192-3-w.sheng@intel.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=lersek@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 11/13/20 03:50, Sheng Wei wrote: > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > index 810985df20..1c6075e332 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > @@ -1111,14 +1140,13 @@ SetPageTableAttributes ( > UINT64 *L3PageTable; > UINT64 *L4PageTable; > UINT64 *L5PageTable; > + UINTN PageTableBase; > BOOLEAN IsSplitted; > BOOLEAN PageTableSplitted; > BOOLEAN CetEnabled; > - IA32_CR4 Cr4; > BOOLEAN Enable5LevelPaging; > > - Cr4.UintN = AsmReadCr4 (); > - Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1); > + GetPageTable (&PageTableBase, &Enable5LevelPaging); > > // > // Don't mark page table memory as read-only if (1) You didn't address point (14) from my v6 review: https://edk2.groups.io/g/devel/message/67251 https://www.redhat.com/archives/edk2-devel-archive/2020-November/msg00410.html To summarize it here: in v8, please move the GetPageTable() call into the outermost loop, as follows: > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > index 1c6075e3326a..cdc1fcefc524 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > @@ -1127,89 +1127,90 @@ SmiPFHandler ( > This function sets memory attribute for page table. > **/ > VOID > SetPageTableAttributes ( > VOID > ) > { > UINTN Index2; > UINTN Index3; > UINTN Index4; > UINTN Index5; > UINT64 *L1PageTable; > UINT64 *L2PageTable; > UINT64 *L3PageTable; > UINT64 *L4PageTable; > UINT64 *L5PageTable; > UINTN PageTableBase; > BOOLEAN IsSplitted; > BOOLEAN PageTableSplitted; > BOOLEAN CetEnabled; > BOOLEAN Enable5LevelPaging; > > - GetPageTable (&PageTableBase, &Enable5LevelPaging); > - > // > // Don't mark page table memory as read-only if > // - no restriction on access to non-SMRAM memory; or > // - SMM heap guard feature enabled; or > // BIT2: SMM page guard enabled > // BIT3: SMM pool guard enabled > // - SMM profile feature enabled > // > if (!mCpuSmmRestrictedMemoryAccess || > ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) || > FeaturePcdGet (PcdCpuSmmProfileEnable)) { > // > // Restriction on access to non-SMRAM memory and heap guard could not be enabled at the same time. > // > ASSERT (!(mCpuSmmRestrictedMemoryAccess && > (PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0)); > > // > // Restriction on access to non-SMRAM memory and SMM profile could not be enabled at the same time. > // > ASSERT (!(mCpuSmmRestrictedMemoryAccess && FeaturePcdGet (PcdCpuSmmProfileEnable))); > return ; > } > > DEBUG ((DEBUG_INFO, "SetPageTableAttributes\n")); > > // > // Disable write protection, because we need mark page table to be write protected. > // We need *write* page table memory, to mark itself to be *read only*. > // > CetEnabled = ((AsmReadCr4() & CR4_CET_ENABLE) != 0) ? TRUE : FALSE; > if (CetEnabled) { > // > // CET must be disabled if WP is disabled. > // > DisableCet(); > } > AsmWriteCr0 (AsmReadCr0() & ~CR0_WP); > > do { > DEBUG ((DEBUG_INFO, "Start...\n")); > PageTableSplitted = FALSE; > L5PageTable = NULL; > + > + GetPageTable (&PageTableBase, &Enable5LevelPaging); > + > if (Enable5LevelPaging) { > L5PageTable = (UINT64 *)PageTableBase; > SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)PageTableBase, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); > PageTableSplitted = (PageTableSplitted || IsSplitted); > } > > for (Index5 = 0; Index5 < (Enable5LevelPaging ? SIZE_4KB/sizeof(UINT64) : 1); Index5++) { > if (Enable5LevelPaging) { > L4PageTable = (UINT64 *)(UINTN)(L5PageTable[Index5] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); > if (L4PageTable == NULL) { > continue; > } > } else { > L4PageTable = (UINT64 *)PageTableBase; > } > SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L4PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); > PageTableSplitted = (PageTableSplitted || IsSplitted); > > for (Index4 = 0; Index4 < SIZE_4KB/sizeof(UINT64); Index4++) { > L3PageTable = (UINT64 *)(UINTN)(L4PageTable[Index4] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); > if (L3PageTable == NULL) { > continue; This incremental patch should be squashed into your v8 2/2. Then I'll give my R-b. Thanks, Laszlo