ODP: [PATCH] MdeModulePkg/AtaAtapiPassThru: Set GHC.AE bitunconditionally for Ahci

[marcin wojtas <mw@semihalf.com>]

Hi Feng,

Sure, good idea.

Best regards,
Marcin

-----Wiadomość oryginalna-----
Od: "Tian, Feng" <feng.tian@intel.com>
Wysłano: ‎2016-‎11-‎24 06:04
Do: "Marcin Wojtas" <mw@semihalf.com>; "edk2-devel@lists.01.org" <edk2-devel@lists.01.org>
DW: "ard.biesheuvel@linaro.org" <ard.biesheuvel@linaro.org>; "leif.lindholm@linaro.org" <leif.lindholm@linaro.org>; "Gao, Liming" <liming.gao@intel.com>; "Kinney, Michael D" <michael.d.kinney@intel.com>; "Tian, Feng" <feng.tian@intel.com>
Temat: RE: [edk2] [PATCH] MdeModulePkg/AtaAtapiPassThru: Set GHC.AE bitunconditionally for Ahci

Marcin

I am ok with removing CAP.SAM check. But the logic will always set GHC.AE bit. Shall we set GHC.AE only if it's 0?

Thanks
Feng

-----Original Message-----
From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Marcin Wojtas
Sent: Wednesday, November 23, 2016 10:59 PM
To: edk2-devel@lists.01.org
Cc: Tian, Feng <feng.tian@intel.com>; ard.biesheuvel@linaro.org; leif.lindholm@linaro.org; Gao, Liming <liming.gao@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>
Subject: [edk2] [PATCH] MdeModulePkg/AtaAtapiPassThru: Set GHC.AE bit unconditionally for Ahci

According to AHCI Spec 1.3 GHC.AE bit description:
"The implementation of this bit is dependent upon the value of the CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be read-only and shall have a reset value of '1'."

Being in AhciMode, for proper operation it is required, that GHC.AE bit is always set, before any other AHCI registers are written to. Current AhciMode implementation, both in AhciReset() and AhciModeInitialization() functions, set GHC.AE bit only depending on 'CAP.SAM == 0' condition, assuming (according to the AHCI spec), that otherwise it has to be set anyway. It may however happen, that even if 'CAP.SAM == 1', GHC.AE requires updating by software.

This patch enables setting GHC.AE bit unconditionally in AhciMode, which fixes AHCI support for Marvell Armada 70x0 and 80x0 SoC families. The change is transparent to all other platforms.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Jan Dabros <jsd@semihalf.com>
---
 MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c | 18 ++++--------------
 1 file changed, 4 insertions(+), 14 deletions(-)

diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
index 533d201..6266ff3 100644
--- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
+++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c
@@ -1451,19 +1451,11 @@ AhciReset (
 {
   UINT64                 Delay;
   UINT32                 Value;
-  UINT32                 Capability;
 
   //
-  // Collect AHCI controller information
-  //
-  Capability = AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET);
-  
+  // Enable AE before accessing any AHCI registers.
   //
-  // Enable AE before accessing any AHCI registers if Supports AHCI Mode Only is not set
-  //
-  if ((Capability & EFI_AHCI_CAP_SAM) == 0) {
-    AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
-  }
+  AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
 
   AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET);
 
@@ -2272,11 +2264,9 @@ AhciModeInitialization (
   Capability = AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET);
   
   //
-  // Enable AE before accessing any AHCI registers if Supports AHCI Mode Only is not set
+  // Enable AE before accessing any AHCI registers.
   //
-  if ((Capability & EFI_AHCI_CAP_SAM) == 0) {
-    AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
-  }
+  AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
 
   //
   // Enable 64-bit DMA support in the PCI layer if this controller
--
1.8.3.1

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