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[94.254.146.179]) by smtp.gmail.com with ESMTPSA id 65sm7821759ljb.23.2016.11.23.21.30.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 23 Nov 2016 21:30:09 -0800 (PST) Message-ID: <58367ae1.44012e0a.110c8.1ae2@mx.google.com> MIME-Version: 1.0 To: "Tian, Feng" , "edk2-devel@lists.01.org" Cc: "ard.biesheuvel@linaro.org" , "leif.lindholm@linaro.org" , "Gao, Liming" , "Kinney, Michael D" From: marcin wojtas Date: Thu, 24 Nov 2016 06:30:08 +0100 In-Reply-To: <7F1BAD85ADEA444D97065A60D2E97EE566E53B4C@SHSMSX101.ccr.corp.intel.com> References: <1479913124-7869-1-git-send-email-mw@semihalf.com> <7F1BAD85ADEA444D97065A60D2E97EE566E53B4C@SHSMSX101.ccr.corp.intel.com> X-Content-Filtered-By: Mailman/MimeDel 2.1.21 Subject: ODP: [PATCH] MdeModulePkg/AtaAtapiPassThru: Set GHC.AE bitunconditionally for Ahci X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Nov 2016 05:30:14 -0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Hi Feng, Sure, good idea. Best regards, Marcin -----Wiadomo=C5=9B=C4=87 oryginalna----- Od: "Tian, Feng" Wys=C5=82ano: =E2=80=8E2016-=E2=80=8E11-=E2=80=8E24 06:04 Do: "Marcin Wojtas" ; "edk2-devel@lists.01.org" DW: "ard.biesheuvel@linaro.org" ; "leif.lindholm= @linaro.org" ; "Gao, Liming" ; "Kinney, Michael D" ; "Tian, Feng" Temat: RE: [edk2] [PATCH] MdeModulePkg/AtaAtapiPassThru: Set GHC.AE bitunco= nditionally for Ahci Marcin I am ok with removing CAP.SAM check. But the logic will always set GHC.AE b= it. Shall we set GHC.AE only if it's 0? Thanks Feng -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Marc= in Wojtas Sent: Wednesday, November 23, 2016 10:59 PM To: edk2-devel@lists.01.org Cc: Tian, Feng ; ard.biesheuvel@linaro.org; leif.lindh= olm@linaro.org; Gao, Liming ; Kinney, Michael D Subject: [edk2] [PATCH] MdeModulePkg/AtaAtapiPassThru: Set GHC.AE bit uncon= ditionally for Ahci According to AHCI Spec 1.3 GHC.AE bit description: "The implementation of this bit is dependent upon the value of the CAP.SAM = bit. If CAP.SAM is '0', then GHC.AE shall be read-write and shall have a re= set value of '0'. If CAP.SAM is '1', then AE shall be read-only and shall h= ave a reset value of '1'." Being in AhciMode, for proper operation it is required, that GHC.AE bit is = always set, before any other AHCI registers are written to. Current AhciMod= e implementation, both in AhciReset() and AhciModeInitialization() function= s, set GHC.AE bit only depending on 'CAP.SAM =3D=3D 0' condition, assuming = (according to the AHCI spec), that otherwise it has to be set anyway. It ma= y however happen, that even if 'CAP.SAM =3D=3D 1', GHC.AE requires updating= by software. This patch enables setting GHC.AE bit unconditionally in AhciMode, which fi= xes AHCI support for Marvell Armada 70x0 and 80x0 SoC families. The change = is transparent to all other platforms. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Signed-off-by: Jan Dabros --- MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c b/MdeModulePk= g/Bus/Ata/AtaAtapiPassThru/AhciMode.c index 533d201..6266ff3 100644 --- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c +++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c @@ -1451,19 +1451,11 @@ AhciReset ( { UINT64 Delay; UINT32 Value; - UINT32 Capability; =20 // - // Collect AHCI controller information - // - Capability =3D AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET); - =20 + // Enable AE before accessing any AHCI registers. // - // Enable AE before accessing any AHCI registers if Supports AHCI Mode O= nly is not set - // - if ((Capability & EFI_AHCI_CAP_SAM) =3D=3D 0) { - AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); - } + AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); =20 AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET); =20 @@ -2272,11 +2264,9 @@ AhciModeInitialization ( Capability =3D AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET); =20 // - // Enable AE before accessing any AHCI registers if Supports AHCI Mode O= nly is not set + // Enable AE before accessing any AHCI registers. // - if ((Capability & EFI_AHCI_CAP_SAM) =3D=3D 0) { - AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); - } + AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); =20 // // Enable 64-bit DMA support in the PCI layer if this controller -- 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel