From: "Lendacky, Thomas" <thomas.lendacky@amd.com>
To: Ray Ni <ray.ni@intel.com>, devel@edk2.groups.io
Cc: Eric Dong <eric.dong@intel.com>,
Rahul Kumar <rahul1.kumar@intel.com>,
Michael Roth <michael.roth@amd.com>,
James Bottomley <jejb@linux.ibm.com>, Min Xu <min.m.xu@intel.com>,
Jiewen Yao <jiewen.yao@intel.com>,
Jordan Justen <jordan.l.justen@intel.com>,
Ard Biesheuvel <ardb+tianocore@kernel.org>,
Erdem Aktas <erdemaktas@google.com>,
Gerd Hoffmann <kraxel@redhat.com>
Subject: Re: [PATCH v3 3/5] MpInitLib: Put SEV logic in separate file
Date: Mon, 16 May 2022 08:41:15 -0500 [thread overview]
Message-ID: <58651b60-018c-1a52-495b-f6cf4283eeeb@amd.com> (raw)
In-Reply-To: <20220516071412.359-4-ray.ni@intel.com>
On 5/16/22 02:14, Ray Ni wrote:
> The patch does several simplifications:
> 1. Treat SwitchToRealProc as part of RendezvousFunnelProc.
> So the common logic in MpLib.c doesn't need to be aware of
> SwitchToRealProc.
> As a result, SwitchToRealSize/Offset are removed from
> MP_ASSEMBLY_ADDRESS_MAP.
>
> 2. Move SwitchToRealProc to AmdSev.nasm.
> All other assembly code in AmdSev.nasm is called through
> OneTimeCall.
I hadn't realized that Brijesh made all of the functions in AmdSev.nasm
OneTimeCall functions, so moving the include now actually gets those
"functions" out of the RendezvousFunnelProc function. Looks much cleaner
this way.
Thanks Ray!
Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com>
Tested-by: Tom Lendacky <thomas.lendacky@amd.com>
>
> Signed-off-by: Ray Ni <ray.ni@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Michael Roth <michael.roth@amd.com>
> Cc: James Bottomley <jejb@linux.ibm.com>
> Cc: Min Xu <min.m.xu@intel.com>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Tom Lendacky <thomas.lendacky@amd.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> Cc: Erdem Aktas <erdemaktas@google.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> ---
> .../Library/MpInitLib/Ia32/MpFuncs.nasm | 5 +-
> UefiCpuPkg/Library/MpInitLib/MpEqu.inc | 4 +-
> UefiCpuPkg/Library/MpInitLib/MpLib.c | 13 +-
> UefiCpuPkg/Library/MpInitLib/MpLib.h | 4 +-
> UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm | 148 ++++++++++++++++
> UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 159 +-----------------
> 6 files changed, 161 insertions(+), 172 deletions(-)
>
> diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm
> index 8981c32722..28301bb8f0 100644
> --- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm
> +++ b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm
> @@ -199,7 +199,6 @@ CProcedureInvoke:
> call eax ; Invoke C function
>
> jmp $ ; Never reach here
> -RendezvousFunnelProcEnd:
>
> ;-------------------------------------------------------------------------------------
> ;SwitchToRealProc procedure follows.
> @@ -209,6 +208,8 @@ SwitchToRealProcStart:
> jmp $ ; Never reach here
> SwitchToRealProcEnd:
>
> +RendezvousFunnelProcEnd:
> +
> ;-------------------------------------------------------------------------------------
> ; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfApStack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer);
> ;
> @@ -258,8 +259,6 @@ ASM_PFX(AsmGetAddressMap):
> mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddress], AsmRelocateApLoopStart
> mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSize], AsmRelocateApLoopEnd - AsmRelocateApLoopStart
> mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.ModeTransitionOffset], Flat32Start - RendezvousFunnelProcStart
> - mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealSize], SwitchToRealProcEnd - SwitchToRealProcStart
> - mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealOffset], SwitchToRealProcStart - RendezvousFunnelProcStart
> mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealNoNxOffset], SwitchToRealProcStart - Flat32Start
> mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeOffset], 0
> mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeSize], 0
> diff --git a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc b/UefiCpuPkg/Library/MpInitLib/MpEqu.inc
> index aba53f5720..1cc071cf7b 100644
> --- a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc
> +++ b/UefiCpuPkg/Library/MpInitLib/MpEqu.inc
> @@ -1,5 +1,5 @@
> ;------------------------------------------------------------------------------ ;
> -; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>
> +; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>
> ; SPDX-License-Identifier: BSD-2-Clause-Patent
> ;
> ; Module Name:
> @@ -27,8 +27,6 @@ struc MP_ASSEMBLY_ADDRESS_MAP
> .RelocateApLoopFuncAddress CTYPE_UINTN 1
> .RelocateApLoopFuncSize CTYPE_UINTN 1
> .ModeTransitionOffset CTYPE_UINTN 1
> - .SwitchToRealSize CTYPE_UINTN 1
> - .SwitchToRealOffset CTYPE_UINTN 1
> .SwitchToRealNoNxOffset CTYPE_UINTN 1
> .SwitchToRealPM16ModeOffset CTYPE_UINTN 1
> .SwitchToRealPM16ModeSize CTYPE_UINTN 1
> diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> index d761bdc487..aa0eb9a70b 100644
> --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> @@ -936,8 +936,7 @@ FillExchangeInfoData (
> // EfiBootServicesCode to avoid page fault if NX memory protection is enabled.
> //
> if (CpuMpData->WakeupBufferHigh != 0) {
> - Size = CpuMpData->AddressMap.RendezvousFunnelSize +
> - CpuMpData->AddressMap.SwitchToRealSize -
> + Size = CpuMpData->AddressMap.RendezvousFunnelSize -
> CpuMpData->AddressMap.ModeTransitionOffset;
> CopyMem (
> (VOID *)CpuMpData->WakeupBufferHigh,
> @@ -991,8 +990,7 @@ BackupAndPrepareWakeupBuffer (
> CopyMem (
> (VOID *)CpuMpData->WakeupBuffer,
> (VOID *)CpuMpData->AddressMap.RendezvousFunnelAddress,
> - CpuMpData->AddressMap.RendezvousFunnelSize +
> - CpuMpData->AddressMap.SwitchToRealSize
> + CpuMpData->AddressMap.RendezvousFunnelSize
> );
> }
>
> @@ -1029,7 +1027,6 @@ GetApResetVectorSize (
> UINTN Size;
>
> Size = AddressMap->RendezvousFunnelSize +
> - AddressMap->SwitchToRealSize +
> sizeof (MP_CPU_EXCHANGE_INFO);
>
> return Size;
> @@ -1054,11 +1051,9 @@ AllocateResetVector (
> CpuMpData->WakeupBuffer = GetWakeupBuffer (ApResetVectorSize);
> CpuMpData->MpCpuExchangeInfo = (MP_CPU_EXCHANGE_INFO *)(UINTN)
> (CpuMpData->WakeupBuffer +
> - CpuMpData->AddressMap.RendezvousFunnelSize +
> - CpuMpData->AddressMap.SwitchToRealSize);
> + CpuMpData->AddressMap.RendezvousFunnelSize);
> CpuMpData->WakeupBufferHigh = AllocateCodeBuffer (
> - CpuMpData->AddressMap.RendezvousFunnelSize +
> - CpuMpData->AddressMap.SwitchToRealSize -
> + CpuMpData->AddressMap.RendezvousFunnelSize -
> CpuMpData->AddressMap.ModeTransitionOffset
> );
> //
> diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpInitLib/MpLib.h
> index 59ab960897..974fb76019 100644
> --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h
> +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h
> @@ -1,7 +1,7 @@
> /** @file
> Common header file for MP Initialize Library.
>
> - Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>
> Copyright (c) 2020, AMD Inc. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
> @@ -181,8 +181,6 @@ typedef struct {
> UINT8 *RelocateApLoopFuncAddress;
> UINTN RelocateApLoopFuncSize;
> UINTN ModeTransitionOffset;
> - UINTN SwitchToRealSize;
> - UINTN SwitchToRealOffset;
> UINTN SwitchToRealNoNxOffset;
> UINTN SwitchToRealPM16ModeOffset;
> UINTN SwitchToRealPM16ModeSize;
> diff --git a/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm b/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm
> index 8bb1161fa0..7c2469f9c5 100644
> --- a/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm
> +++ b/UefiCpuPkg/Library/MpInitLib/X64/AmdSev.nasm
> @@ -198,3 +198,151 @@ RestoreGhcb:
>
> SevEsGetApicIdExit:
> OneTimeCallRet SevEsGetApicId
> +
> +
> +;-------------------------------------------------------------------------------------
> +;SwitchToRealProc procedure follows.
> +;ALSO THIS PROCEDURE IS EXECUTED BY APs TRANSITIONING TO 16 BIT MODE. HENCE THIS PROC
> +;IS IN MACHINE CODE.
> +; SwitchToRealProc (UINTN BufferStart, UINT16 Code16, UINT16 Code32, UINTN StackStart)
> +; rcx - Buffer Start
> +; rdx - Code16 Selector Offset
> +; r8 - Code32 Selector Offset
> +; r9 - Stack Start
> +;-------------------------------------------------------------------------------------
> +SwitchToRealProcStart:
> +BITS 64
> + cli
> +
> + ;
> + ; Get RDX reset value before changing stacks since the
> + ; new stack won't be able to accomodate a #VC exception.
> + ;
> + push rax
> + push rbx
> + push rcx
> + push rdx
> +
> + mov rax, 1
> + cpuid
> + mov rsi, rax ; Save off the reset value for RDX
> +
> + pop rdx
> + pop rcx
> + pop rbx
> + pop rax
> +
> + ;
> + ; Establish stack below 1MB
> + ;
> + mov rsp, r9
> +
> + ;
> + ; Push ultimate Reset Vector onto the stack
> + ;
> + mov rax, rcx
> + shr rax, 4
> + push word 0x0002 ; RFLAGS
> + push ax ; CS
> + push word 0x0000 ; RIP
> + push word 0x0000 ; For alignment, will be discarded
> +
> + ;
> + ; Get address of "16-bit operand size" label
> + ;
> + lea rbx, [PM16Mode]
> +
> + ;
> + ; Push addresses used to change to compatibility mode
> + ;
> + lea rax, [CompatMode]
> + push r8
> + push rax
> +
> + ;
> + ; Clear R8 - R15, for reset, before going into 32-bit mode
> + ;
> + xor r8, r8
> + xor r9, r9
> + xor r10, r10
> + xor r11, r11
> + xor r12, r12
> + xor r13, r13
> + xor r14, r14
> + xor r15, r15
> +
> + ;
> + ; Far return into 32-bit mode
> + ;
> + retfq
> +
> +BITS 32
> +CompatMode:
> + ;
> + ; Set up stack to prepare for exiting protected mode
> + ;
> + push edx ; Code16 CS
> + push ebx ; PM16Mode label address
> +
> + ;
> + ; Disable paging
> + ;
> + mov eax, cr0 ; Read CR0
> + btr eax, 31 ; Set PG=0
> + mov cr0, eax ; Write CR0
> +
> + ;
> + ; Disable long mode
> + ;
> + mov ecx, 0c0000080h ; EFER MSR number
> + rdmsr ; Read EFER
> + btr eax, 8 ; Set LME=0
> + wrmsr ; Write EFER
> +
> + ;
> + ; Disable PAE
> + ;
> + mov eax, cr4 ; Read CR4
> + btr eax, 5 ; Set PAE=0
> + mov cr4, eax ; Write CR4
> +
> + mov edx, esi ; Restore RDX reset value
> +
> + ;
> + ; Switch to 16-bit operand size
> + ;
> + retf
> +
> +BITS 16
> + ;
> + ; At entry to this label
> + ; - RDX will have its reset value
> + ; - On the top of the stack
> + ; - Alignment data (two bytes) to be discarded
> + ; - IP for Real Mode (two bytes)
> + ; - CS for Real Mode (two bytes)
> + ;
> + ; This label is also used with AsmRelocateApLoop. During MP finalization,
> + ; the code from PM16Mode to SwitchToRealProcEnd is copied to the start of
> + ; the WakeupBuffer, allowing a parked AP to be booted by an OS.
> + ;
> +PM16Mode:
> + mov eax, cr0 ; Read CR0
> + btr eax, 0 ; Set PE=0
> + mov cr0, eax ; Write CR0
> +
> + pop ax ; Discard alignment data
> +
> + ;
> + ; Clear registers (except RDX and RSP) before going into 16-bit mode
> + ;
> + xor eax, eax
> + xor ebx, ebx
> + xor ecx, ecx
> + xor esi, esi
> + xor edi, edi
> + xor ebp, ebp
> +
> + iret
> +
> +SwitchToRealProcEnd:
> diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
> index d7e0e1fabd..1daaa72b1e 100644
> --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
> +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
> @@ -152,11 +152,6 @@ SkipEnable5LevelPaging:
>
> BITS 64
>
> -;
> -; Required for the AMD SEV helper functions
> -;
> -%include "AmdSev.nasm"
> -
> LongModeStart:
> mov esi, ebx
> lea edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD (InitFlag)]
> @@ -265,154 +260,12 @@ CProcedureInvoke:
> add rsp, 20h
> jmp $ ; Should never reach here
>
> -RendezvousFunnelProcEnd:
> -
> -;-------------------------------------------------------------------------------------
> -;SwitchToRealProc procedure follows.
> -;ALSO THIS PROCEDURE IS EXECUTED BY APs TRANSITIONING TO 16 BIT MODE. HENCE THIS PROC
> -;IS IN MACHINE CODE.
> -; SwitchToRealProc (UINTN BufferStart, UINT16 Code16, UINT16 Code32, UINTN StackStart)
> -; rcx - Buffer Start
> -; rdx - Code16 Selector Offset
> -; r8 - Code32 Selector Offset
> -; r9 - Stack Start
> -;-------------------------------------------------------------------------------------
> -SwitchToRealProcStart:
> -BITS 64
> - cli
> -
> - ;
> - ; Get RDX reset value before changing stacks since the
> - ; new stack won't be able to accomodate a #VC exception.
> - ;
> - push rax
> - push rbx
> - push rcx
> - push rdx
> -
> - mov rax, 1
> - cpuid
> - mov rsi, rax ; Save off the reset value for RDX
> -
> - pop rdx
> - pop rcx
> - pop rbx
> - pop rax
> -
> - ;
> - ; Establish stack below 1MB
> - ;
> - mov rsp, r9
> -
> - ;
> - ; Push ultimate Reset Vector onto the stack
> - ;
> - mov rax, rcx
> - shr rax, 4
> - push word 0x0002 ; RFLAGS
> - push ax ; CS
> - push word 0x0000 ; RIP
> - push word 0x0000 ; For alignment, will be discarded
> -
> - ;
> - ; Get address of "16-bit operand size" label
> - ;
> - lea rbx, [PM16Mode]
> -
> - ;
> - ; Push addresses used to change to compatibility mode
> - ;
> - lea rax, [CompatMode]
> - push r8
> - push rax
> -
> - ;
> - ; Clear R8 - R15, for reset, before going into 32-bit mode
> - ;
> - xor r8, r8
> - xor r9, r9
> - xor r10, r10
> - xor r11, r11
> - xor r12, r12
> - xor r13, r13
> - xor r14, r14
> - xor r15, r15
> -
> - ;
> - ; Far return into 32-bit mode
> - ;
> - retfq
> -
> -BITS 32
> -CompatMode:
> - ;
> - ; Set up stack to prepare for exiting protected mode
> - ;
> - push edx ; Code16 CS
> - push ebx ; PM16Mode label address
> -
> - ;
> - ; Disable paging
> - ;
> - mov eax, cr0 ; Read CR0
> - btr eax, 31 ; Set PG=0
> - mov cr0, eax ; Write CR0
> -
> - ;
> - ; Disable long mode
> - ;
> - mov ecx, 0c0000080h ; EFER MSR number
> - rdmsr ; Read EFER
> - btr eax, 8 ; Set LME=0
> - wrmsr ; Write EFER
> -
> - ;
> - ; Disable PAE
> - ;
> - mov eax, cr4 ; Read CR4
> - btr eax, 5 ; Set PAE=0
> - mov cr4, eax ; Write CR4
> -
> - mov edx, esi ; Restore RDX reset value
> -
> - ;
> - ; Switch to 16-bit operand size
> - ;
> - retf
> -
> -BITS 16
> - ;
> - ; At entry to this label
> - ; - RDX will have its reset value
> - ; - On the top of the stack
> - ; - Alignment data (two bytes) to be discarded
> - ; - IP for Real Mode (two bytes)
> - ; - CS for Real Mode (two bytes)
> - ;
> - ; This label is also used with AsmRelocateApLoop. During MP finalization,
> - ; the code from PM16Mode to SwitchToRealProcEnd is copied to the start of
> - ; the WakeupBuffer, allowing a parked AP to be booted by an OS.
> - ;
> -PM16Mode:
> - mov eax, cr0 ; Read CR0
> - btr eax, 0 ; Set PE=0
> - mov cr0, eax ; Write CR0
> -
> - pop ax ; Discard alignment data
> -
> - ;
> - ; Clear registers (except RDX and RSP) before going into 16-bit mode
> - ;
> - xor eax, eax
> - xor ebx, ebx
> - xor ecx, ecx
> - xor esi, esi
> - xor edi, edi
> - xor ebp, ebp
> -
> - iret
> +;
> +; Required for the AMD SEV helper functions
> +;
> +%include "AmdSev.nasm"
>
> -SwitchToRealProcEnd:
> +RendezvousFunnelProcEnd:
>
> ;-------------------------------------------------------------------------------------
> ; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfApStack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer);
> @@ -596,8 +449,6 @@ ASM_PFX(AsmGetAddressMap):
> mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddress], rax
> mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSize], AsmRelocateApLoopEnd - AsmRelocateApLoopStart
> mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.ModeTransitionOffset], Flat32Start - RendezvousFunnelProcStart
> - mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealSize], SwitchToRealProcEnd - SwitchToRealProcStart
> - mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealOffset], SwitchToRealProcStart - RendezvousFunnelProcStart
> mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealNoNxOffset], SwitchToRealProcStart - Flat32Start
> mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeOffset], PM16Mode - RendezvousFunnelProcStart
> mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeSize], SwitchToRealProcEnd - PM16Mode
next prev parent reply other threads:[~2022-05-16 13:41 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-16 7:14 [PATCH v3 0/5] MpInitLib code refactoring Ni, Ray
2022-05-16 7:14 ` [PATCH v3 1/5] MpInitLib: Allocate code buffer for PEI phase Ni, Ray
2022-05-16 7:14 ` [PATCH v3 2/5] MpInitLib: remove unneeded global ASM_PFX Ni, Ray
2022-05-16 7:14 ` [PATCH v3 3/5] MpInitLib: Put SEV logic in separate file Ni, Ray
2022-05-16 13:41 ` Lendacky, Thomas [this message]
2022-05-16 7:14 ` [PATCH v3 4/5] MpInitLib: Only allocate below 1MB memory for 16bit code Ni, Ray
2022-05-16 7:14 ` [PATCH v3 5/5] MpInitLib: Move the Above1Mb vector allocation to MpInitLibInitialize Ni, Ray
2022-06-10 8:19 ` [edk2-devel] [PATCH v3 0/5] MpInitLib code refactoring Dong, Eric
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=58651b60-018c-1a52-495b-f6cf4283eeeb@amd.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox