From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-1.mimecast.com (us-smtp-1.mimecast.com [207.211.31.81]) by mx.groups.io with SMTP id smtpd.web11.28071.1595449685991302947 for ; Wed, 22 Jul 2020 13:28:06 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=YZUpYZ6r; spf=pass (domain: redhat.com, ip: 207.211.31.81, mailfrom: lersek@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1595449685; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wKCe25iKiFu7beDwOGW5wKoJiHAJg8ZY91FPrqYGl4Y=; b=YZUpYZ6r1ZrQE+hzB7BHJk3qPbb2EYCzJYBFl96/gMEhPvBAtUso30M199MXTY9W7ZvCg5 WDqCPmfYa9yMcNtlGx6Bg4unp+JREaBGvDPP6HlU987Z7PHrnPZbmkGnApOMCB7cETD9PR 8xrWah8aQ/RSsiKWEL+LZ0PHphQKIWQ= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-19-YB3WJ28TPRW0JZWEB8ke6g-1; Wed, 22 Jul 2020 16:27:57 -0400 X-MC-Unique: YB3WJ28TPRW0JZWEB8ke6g-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id BF568107ACCA; Wed, 22 Jul 2020 20:27:55 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-113-129.ams2.redhat.com [10.36.113.129]) by smtp.corp.redhat.com (Postfix) with ESMTP id 2C9ED5D9CD; Wed, 22 Jul 2020 20:27:52 +0000 (UTC) Subject: Re: [edk2-devel] [PATCH v11 06/46] MdePkg/BaseLib: Add support for the XGETBV instruction To: "Liu, Zhiguang" , "devel@edk2.groups.io" , "thomas.lendacky@amd.com" Cc: Brijesh Singh , Ard Biesheuvel , "Dong, Eric" , "Justen, Jordan L" , "Gao, Liming" , "Kinney, Michael D" , "Ni, Ray" References: <0d091f43ae96ca4617f6a95a018bfaed6280eec2.1595366363.git.thomas.lendacky@amd.com> From: "Laszlo Ersek" Message-ID: <59baa2d3-69e0-2f98-27b8-92010f393109@redhat.com> Date: Wed, 22 Jul 2020 22:27:52 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Firefox/52.0 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=lersek@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit On 07/22/20 02:55, Liu, Zhiguang wrote: > Hi Tom, > Nasm is a cross-OS assembly code and can be used in Linux. > So I think we don't need implement the same function in GccInline.c, we can just use the nasm file in Linux. I could agree, but this would create an inconsistency with the existent functions (where both gcc inline assembly and NASM exists). For example, consider AsmReadEflags(): - inline assembly for MSFT IA32 ("Ia32/ReadEflags.c") - NASM for MSFT X64 ("X64/ReadEflags.nasm") - inline assembly for GCC IA32 ("Ia32/GccInline.c") - inline assembly for GCC X64 ("X64/GccInline.c") The source file "X64/ReadEflags.nasm" could be used with GCC X64 too, not just with MSFT X64. So why do we have the gcc inline implementation for AsmReadEflags() in "X64/GccInline.c", in the first place? The pattern that a contributor is supposed to follow is not clear to me. Thanks, Laszlo >> -----Original Message----- >> From: devel@edk2.groups.io On Behalf Of >> Lendacky, Thomas >> Sent: Wednesday, July 22, 2020 5:19 AM >> To: devel@edk2.groups.io >> Cc: Brijesh Singh ; Ard Biesheuvel >> ; Dong, Eric ; Justen, >> Jordan L ; Laszlo Ersek ; >> Gao, Liming ; Kinney, Michael D >> ; Ni, Ray >> Subject: [edk2-devel] [PATCH v11 06/46] MdePkg/BaseLib: Add support for >> the XGETBV instruction >> >> From: Tom Lendacky >> >> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 >> >> Under SEV-ES, a CPUID instruction requires the current value of the XCR0 >> register. In order to retrieve that value, the XGETBV instruction needs >> to be executed. >> >> Provide the necessary support to execute the XGETBV instruction. >> >> Cc: Michael D Kinney >> Cc: Liming Gao >> Signed-off-by: Tom Lendacky >> --- >> MdePkg/Library/BaseLib/BaseLib.inf | 2 ++ >> MdePkg/Include/Library/BaseLib.h | 17 +++++++++++++ >> MdePkg/Library/BaseLib/Ia32/GccInline.c | 28 ++++++++++++++++++++ >> MdePkg/Library/BaseLib/X64/GccInline.c | 30 ++++++++++++++++++++++ >> MdePkg/Library/BaseLib/Ia32/XGetBv.nasm | 31 >> ++++++++++++++++++++++ >> MdePkg/Library/BaseLib/X64/XGetBv.nasm | 34 >> +++++++++++++++++++++++++ >> 6 files changed, 142 insertions(+) >> create mode 100644 MdePkg/Library/BaseLib/Ia32/XGetBv.nasm >> create mode 100644 MdePkg/Library/BaseLib/X64/XGetBv.nasm >> >> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf >> b/MdePkg/Library/BaseLib/BaseLib.inf >> index c740a819cacf..e26c0d8cb0ac 100644 >> --- a/MdePkg/Library/BaseLib/BaseLib.inf >> +++ b/MdePkg/Library/BaseLib/BaseLib.inf >> @@ -153,6 +153,7 @@ [Sources.Ia32] >> Ia32/ARShiftU64.c | MSFT >> Ia32/EnableCache.c | MSFT >> Ia32/DisableCache.c | MSFT >> + Ia32/XGetBv.nasm | MSFT >> >> >> Ia32/GccInline.c | GCC >> @@ -288,6 +289,7 @@ [Sources.X64] >> X64/ReadCr2.nasm| MSFT >> X64/ReadCr0.nasm| MSFT >> X64/ReadEflags.nasm| MSFT >> + X64/XGetBv.nasm | MSFT >> >> >> X64/Non-existing.c >> diff --git a/MdePkg/Include/Library/BaseLib.h >> b/MdePkg/Include/Library/BaseLib.h >> index 8e7b87cbda4e..7edf0051a0a0 100644 >> --- a/MdePkg/Include/Library/BaseLib.h >> +++ b/MdePkg/Include/Library/BaseLib.h >> @@ -7831,6 +7831,23 @@ AsmLfence ( >> VOID >> ); >> >> +/** >> + Executes a XGETBV instruction >> + >> + Executes a XGETBV instruction. This function is only available on IA-32 and >> + x64. >> + >> + @param[in] Index Extended control register index >> + >> + @return The current value of the extended control register >> +**/ >> +UINT64 >> +EFIAPI >> +AsmXGetBv ( >> + IN UINT32 Index >> + ); >> + >> + >> /** >> Patch the immediate operand of an IA32 or X64 instruction such that the >> byte, >> word, dword or qword operand is encoded at the end of the instruction's >> diff --git a/MdePkg/Library/BaseLib/Ia32/GccInline.c >> b/MdePkg/Library/BaseLib/Ia32/GccInline.c >> index 6ed938187a08..c2565ab9a183 100644 >> --- a/MdePkg/Library/BaseLib/Ia32/GccInline.c >> +++ b/MdePkg/Library/BaseLib/Ia32/GccInline.c >> @@ -584,3 +584,31 @@ AsmReadTsc ( >> >> return Data; >> } >> + >> + >> +/** >> + Executes a XGETBV instruction >> + >> + Executes a XGETBV instruction. This function is only available on IA-32 and >> + x64. >> + >> + @param[in] Index Extended control register index >> + >> + @return The current value of the extended control register >> +**/ >> +UINT64 >> +EFIAPI >> +AsmXGetBv ( >> + IN UINT32 Index >> + ) >> +{ >> + UINT64 Data; >> + >> + __asm__ __volatile__ ( >> + "xgetbv" >> + : "=A" (Data) >> + : "c" (Index) >> + ); >> + >> + return Data; >> +} >> diff --git a/MdePkg/Library/BaseLib/X64/GccInline.c >> b/MdePkg/Library/BaseLib/X64/GccInline.c >> index 40a208f1985f..65f864e35922 100644 >> --- a/MdePkg/Library/BaseLib/X64/GccInline.c >> +++ b/MdePkg/Library/BaseLib/X64/GccInline.c >> @@ -560,3 +560,33 @@ AsmReadTsc ( >> >> return (((UINT64)HiData) << 32) | LowData; >> } >> + >> + >> +/** >> + Executes a XGETBV instruction >> + >> + Executes a XGETBV instruction. This function is only available on IA-32 and >> + x64. >> + >> + @param[in] Index Extended control register index >> + >> + @return The current value of the extended control register >> +**/ >> +UINT64 >> +EFIAPI >> +AsmXGetBv ( >> + IN UINT32 Index >> + ) >> +{ >> + UINT32 LowData; >> + UINT32 HighData; >> + >> + __asm__ __volatile__ ( >> + "xgetbv" >> + : "=a" (LowData), >> + "=d" (HighData) >> + : "c" (Index) >> + ); >> + >> + return (((UINT64)HighData) << 32) | LowData; >> +} >> diff --git a/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm >> b/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm >> new file mode 100644 >> index 000000000000..9f7b03bbff35 >> --- /dev/null >> +++ b/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm >> @@ -0,0 +1,31 @@ >> +;------------------------------------------------------------------------------ >> +; >> +; Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.
>> +; SPDX-License-Identifier: BSD-2-Clause-Patent >> +; >> +; Module Name: >> +; >> +; XGetBv.Asm >> +; >> +; Abstract: >> +; >> +; AsmXgetBv function >> +; >> +; Notes: >> +; >> +;------------------------------------------------------------------------------ >> + >> + SECTION .text >> + >> +;------------------------------------------------------------------------------ >> +; UINT64 >> +; EFIAPI >> +; AsmXGetBv ( >> +; IN UINT32 Index >> +; ); >> +;------------------------------------------------------------------------------ >> +global ASM_PFX(AsmXGetBv) >> +ASM_PFX(AsmXGetBv): >> + mov ecx, [esp + 4] >> + xgetbv >> + ret >> diff --git a/MdePkg/Library/BaseLib/X64/XGetBv.nasm >> b/MdePkg/Library/BaseLib/X64/XGetBv.nasm >> new file mode 100644 >> index 000000000000..09f3be8ae0a8 >> --- /dev/null >> +++ b/MdePkg/Library/BaseLib/X64/XGetBv.nasm >> @@ -0,0 +1,34 @@ >> +;------------------------------------------------------------------------------ >> +; >> +; Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.
>> +; SPDX-License-Identifier: BSD-2-Clause-Patent >> +; >> +; Module Name: >> +; >> +; XGetBv.Asm >> +; >> +; Abstract: >> +; >> +; AsmXgetBv function >> +; >> +; Notes: >> +; >> +;------------------------------------------------------------------------------ >> + >> + DEFAULT REL >> + SECTION .text >> + >> +;------------------------------------------------------------------------------ >> +; UINT64 >> +; EFIAPI >> +; AsmXGetBv ( >> +; IN UINT32 Index >> +; ); >> +;------------------------------------------------------------------------------ >> +global ASM_PFX(AsmXGetBv) >> +ASM_PFX(AsmXGetBv): >> + xgetbv >> + shl rdx, 32 >> + or rax, rdx >> + ret >> + >> -- >> 2.27.0 >> >> >> >