From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from loongson.cn (loongson.cn [114.242.206.163]) by mx.groups.io with SMTP id smtpd.web11.97643.1680603286310294450 for ; Tue, 04 Apr 2023 03:14:46 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: loongson.cn, ip: 114.242.206.163, mailfrom: lichao@loongson.cn) Received: from loongson.cn (unknown [10.40.24.149]) by gateway (Coremail) with SMTP id _____8DxEzSS+Ctk62IWAA--.34691S3; Tue, 04 Apr 2023 18:14:42 +0800 (CST) Received: from [10.40.24.149] (unknown [10.40.24.149]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Cxfb6S+CtkyiUVAA--.44486S3; Tue, 04 Apr 2023 18:14:42 +0800 (CST) Message-ID: <59bad058-81fc-cd19-b5f0-f9214d7816a8@loongson.cn> Date: Tue, 4 Apr 2023 18:14:42 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 From: "Chao Li" To: devel@edk2.groups.io, Michael D Kinney , Liming Gao , ray.ni@intel.com, Sunil V L , andrei.warkentin@intel.com Subject: About the way of exception registration X-CM-TRANSID: AQAAf8Cxfb6S+CtkyiUVAA--.44486S3 X-CM-SenderInfo: xolfxt3r6o00pqjv00gofq/1tbiAQALCGQqwfgU0gABsy X-Coremail-Antispam: 1Uk129KBjvJXoW7KFy7Wr4UWr1DKryrJF4kXrb_yoW8Xw43pr 4293s3Crs5Jr1I93yUAw409FyrKFW8J3y5Grn5Xwn0qwn3KFy0vr4rtFWUAa1Uur47Jr1j va4rAFnYg3y5ArJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj DUYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUUbzxYFVCjjxCrM7AC8VAFwI0_Jr0_ Gr1l1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s1l1IIY67AEw4v_JrI_Jryl8cAvFV AK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVWUJVWUCwA2 z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr 1l84ACjcxK6I8E87Iv6xkF7I0E14v26F4UJVW0owAS0I0E0xvYzxvE52x082IY62kv0487 Mc804VCY07AIYIkI8VC2zVCFFI0UMcIj6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67 AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IY64vIr41lc7I2V7IY0VAS07Al zVAYIcxG8wCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F4 0E14v26r106r1rMI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1l IxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxV AFwI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j 6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU1Au4U UUUUU== Content-Type: multipart/alternative; boundary="------------KOAXQ41DjfBgZov0g48J50fV" --------------KOAXQ41DjfBgZov0g48J50fV Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi all, I'm going porting LoongArch64 to UefiCpuPkg and OvmfPkg. A problem is blocked me that EFI_CPU_ARCH_PROTOCOL only provides interrupt register method, no exception register method. I found that RISC-V hase the same issue, Andrei modified DebugSupport.h to fix it, commitid:69da506c927f8092ea8f783a092a694a3582e3ef. But this way may be not comply with UEFI SPEC, because in section 18 of UEFI SPEC, different architectures have been defined interupt types and exception types, and modifications like Andrei's will cause the UEFI SPEC and DebugSupport.h content to not match. I also checked in AARCH64, they don't have this problem, because in AARCH64(ARM) uses synchronous exception, this exception is CPU internal exeption entry point, different type can separated by this entry point. So they just register this synchronous exception is fine,  and the exception filtering will be handled by the synchronous exception handler. I think we need a way to reigster the exception, because some architectures like RISC-V and LoongArch don't have synchronous exception, and some one want to register exceptions to do some different. Can we add exception registration method at the end of EFI_CPU_ARCH_PROTOCOL? If not, I think there is only a modifcation like Andrei's, when the interrupt type and exception type use same numbers, put a flag in the highest bit to distinguish them. But I don't think this way is very suitable, just like above I talk about. Hope to know your thoughts and look forward to hearing from you! Thanks, Chao --------------KOAXQ41DjfBgZov0g48J50fV Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 8bit

Hi all,

I'm going porting LoongArch64 to UefiCpuPkg and OvmfPkg. A problem is blocked me that EFI_CPU_ARCH_PROTOCOL only provides interrupt register method, no exception register method.

I found that RISC-V hase the same issue, Andrei modified DebugSupport.h to fix it, commitid:69da506c927f8092ea8f783a092a694a3582e3ef. But this way may be not comply with UEFI SPEC, because in section 18 of UEFI SPEC, different architectures have been defined interupt types and exception types, and modifications like Andrei's will cause the UEFI SPEC and DebugSupport.h content to not match.

I also checked in AARCH64, they don't have this problem, because in AARCH64(ARM) uses synchronous exception, this exception is CPU internal exeption entry point, different type can separated by this entry point. So they just register this synchronous exception is fine,  and the exception filtering will be handled by the synchronous exception handler.

I think we need a way to reigster the exception, because some architectures like RISC-V and LoongArch don't have synchronous exception, and some one want to register exceptions to do some different. Can we add exception registration method at the end of EFI_CPU_ARCH_PROTOCOL? If not, I think there is only a modifcation like Andrei's, when the interrupt type and exception type use same numbers, put a flag in the highest bit to distinguish them. But I don't think this way is very suitable, just like above I talk about.

Hope to know your thoughts and look forward to hearing from you!



Thanks,
Chao
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