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From: "PierreGondois" <pierre.gondois@arm.com>
To: Jeshua Smith <jeshuas@nvidia.com>, devel@edk2.groups.io
Cc: Sami.Mujawar@arm.com, quic_llindhol@quicinc.com,
	ardb+tianocore@kernel.org
Subject: Re: [edk2-devel] [PATCH] DynamicTablesPkg/AmlLib: Enumerate memory cacheability and\r type
Date: Tue, 3 Oct 2023 09:03:42 +0200	[thread overview]
Message-ID: <5a8510b3-91cf-385c-9706-0d32b8b49dcc@arm.com> (raw)
In-Reply-To: <4e29533888e7dbc72d0815aa4318230636a43588.1696283429.git.jeshuas@nvidia.com>

Hello Jeshua,
just a few NITs:

On 10/2/23 23:52, Jeshua Smith wrote:
> AmlCodeGenRdQWordMemory's and AmlCodeGenRdDWordMemory's Cacheable
> and MemoryRangeType parameters treat specific values as having
> specific meanings. This change adds enums to map those meanings to their
> corresponding values.
> 
> Signed-off-by: Jeshua Smith <jeshuas@nvidia.com>
> ---
>   .../Include/Library/AmlLib/AmlLib.h           | 33 +++++++++++++++++++
>   .../AcpiSsdtPcieLibArm/SsdtPcieGenerator.c    | 12 +++----
>   2 files changed, 39 insertions(+), 6 deletions(-)
> 
> diff --git a/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h b/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h
> index 510c79a399..6a273059fb 100644
> --- a/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h
> +++ b/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h
> @@ -59,6 +59,39 @@ typedef void *AML_DATA_NODE_HANDLE;
>   
>   #endif // AML_HANDLE
>   
> +/** Cacheable parameter values
> +
> +  Possible values are:
> +    0-The memory is non-cacheable
> +    1-The memory is cacheable
> +    2-The memory is cacheable and supports
> +      write combining
> +    3-The memory is cacheable and prefetchable

Is it possible add a reference to ACPI 6.5, s6.4.3.5.5 "Resource Type
Specific Flags" for future reference ? Same comment for the other enum.

> +
> +**/
> +typedef enum {
> +  AML_MEMORY_NONCACHEABLE = 0,
> +  AML_MEMORY_CACHEABLE    = 1,
> +  AML_MEMORY_CACHEABLE_WC = 2,
> +  AML_MEMORY_CACHEABLE_PF = 3

Just for a matter of unification in the package, is is possible to
use camelcase enum names, like AmlMemoryNonCacheable ?
Also would it be possible to add a AmlMemoryMax enum at the end ?
Same comment for the other enum.

> +} AML_MEMORY_CACHEABILITY;
> +
> +/** MemoryRangeType parameter values
> +
> +  Possible values are:
> +    0-AddressRangeMemory
> +    1-AddressRangeReserved
> +    2-AddressRangeACPI
> +    3-AddressRangeNVS
> +
> +**/
> +typedef enum {
> +  AML_MEMORY_RANGE_TYPE_MEMORY   = 0,
> +  AML_MEMORY_RANGE_TYPE_RESERVED = 1,
> +  AML_MEMORY_RANGE_TYPE_ACPI     = 2,
> +  AML_MEMORY_RANGE_TYPE_NVS      = 3
> +} AML_MEMORY_RANGE_TYPE;
> +
>   /** Parse the definition block.
>   
>     The function parses the whole AML blob. It starts with the ACPI DSDT/SSDT
> diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c
> index 9ddaddc198..7df7117352 100644
> --- a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c
> +++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c

Is is possible to modify the definition/declaration of the modified functions
to use the newly created type ?

> @@ -566,7 +566,7 @@ GeneratePciCrs (
>                      IsPosDecode,
>                      TRUE,
>                      TRUE,
> -                   TRUE,
> +                   AML_MEMORY_CACHEABLE,
>                      TRUE,
>                      0,
>                      AddrMapInfo->PciAddress,
> @@ -575,7 +575,7 @@ GeneratePciCrs (
>                      AddrMapInfo->AddressSize,
>                      0,
>                      NULL,
> -                   0,
> +                   AML_MEMORY_RANGE_TYPE_MEMORY,
>                      TRUE,
>                      CrsNode,
>                      NULL
> @@ -588,7 +588,7 @@ GeneratePciCrs (
>                      IsPosDecode,
>                      TRUE,
>                      TRUE,
> -                   TRUE,
> +                   AML_MEMORY_CACHEABLE,
>                      TRUE,
>                      0,
>                      AddrMapInfo->PciAddress,
> @@ -597,7 +597,7 @@ GeneratePciCrs (
>                      AddrMapInfo->AddressSize,
>                      0,
>                      NULL,
> -                   0,
> +                   AML_MEMORY_RANGE_TYPE_MEMORY,
>                      TRUE,
>                      CrsNode,
>                      NULL
> @@ -718,7 +718,7 @@ ReserveEcamSpace (
>                TRUE,
>                TRUE,
>                TRUE,
> -             FALSE,  // non-cacheable
> +             AML_MEMORY_NONCACHEABLE,
>                TRUE,
>                0,
>                AddressMinimum,
> @@ -727,7 +727,7 @@ ReserveEcamSpace (
>                AddressMaximum - AddressMinimum + 1,
>                0,
>                NULL,
> -             0,
> +             AML_MEMORY_RANGE_TYPE_MEMORY,
>                TRUE,
>                CrsNode,
>                NULL

Regards,
Pierre


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  reply	other threads:[~2023-10-03  7:04 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-02 21:52 [edk2-devel] [PATCH] DynamicTablesPkg/AmlLib: Enumerate memory cacheability and type Jeshua Smith via groups.io
2023-10-03  7:03 ` PierreGondois [this message]
2023-10-03 15:22 ` Leif Lindholm

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