From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from hqnvemgate25.nvidia.com (hqnvemgate25.nvidia.com [216.228.121.64]) by mx.groups.io with SMTP id smtpd.web12.3772.1591413809374039597 for ; Fri, 05 Jun 2020 20:23:29 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nvidia.com header.s=n1 header.b=dwCpOHiv; spf=pass (domain: nvidia.com, ip: 216.228.121.64, mailfrom: ipark@nvidia.com) Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 05 Jun 2020 20:22:00 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 05 Jun 2020 20:23:28 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 05 Jun 2020 20:23:28 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sat, 6 Jun 2020 03:23:28 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sat, 6 Jun 2020 03:23:28 +0000 Received: from ipark-ubuntu.nvidia.com (Not Verified[10.28.100.106]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 05 Jun 2020 20:23:28 -0700 From: "Irene Park" To: CC: Irene Park Subject: [PATCH] ArmPlatformPkg/PL011UartLib: Add PCD for FIFO depth Date: Fri, 5 Jun 2020 23:23:24 -0400 Message-ID: <5a94d7db2db04a22baa79c65d42feeea30bf81b8.1591413682.git.ipark@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public Return-Path: ipark@nvidia.com MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591413720; bh=xIosOavfN3B8uHxQtY5R4UvjzfjjHwDd9lEWS78M/10=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=dwCpOHivlI9OjNzRc9tyoR9fkKsDXoSkek2eZLRFvEWZD6cawob8R/A+J9qeQhdQK 370vqYYIKOvjyl88IT9aJkImzCytpfQGdD0/sJR3Rm2PzL6VnlZFM1rcdUuTXnHi2j nzZBTZmjiOliGQ5jw3Qx5KE36ot4g5wzQP/LX2FSyveW+hqswmwqZMvJ9m2/AkCvm5 kzn9Cx8qymunZw4lXN4U0H0FhEoS3gHrHU1c9dSdqGadZHtzXpHRWeMA0pzraQ4Yt/ oQnbaIi2mM/Eq6DlL1d4THcVP419lrqh8dpxPWWXx3HzGL2oEvq/MFxqPHDNIT32cy O/jxUz2S3pt2Q== Content-Type: text/plain From: Irene Park PL011UartLib determines its FIFO depth based on the PID2 value but the register PID2 is not mandatory in the SBSA spec. This change adds a new 32bit PCD reference to define a FIFO depth and make PL011UartLib available for the custom UART which is compliant to the SBSA spec but doesn't support the optional register of PID2. * Available values for PL011UartFifoDepth: 0, 16, 32 Note that a FIFO depth will be determined based on PID2 when the PCD reference is set to 0. Signed-off-by: Irene Park --- ArmPlatformPkg/ArmPlatformPkg.dec | 2 ++ ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c | 4 ++++ ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf | 1 + 3 files changed, 7 insertions(+) diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec index 696d636..b4b950f 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -72,6 +72,8 @@ gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant|0|UINT8|0x0000003E + ## FIFO Depth in 0/16/32 (0 to determine FIFO depth based on PID2) + gArmPlatformTokenSpaceGuid.PL011UartFifoDepth|0|UINT32|0x0000003F ## PL011 Serial Debug UART gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030 diff --git a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c index 801990d..1aa6830 100644 --- a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c +++ b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c @@ -79,9 +79,13 @@ PL011UartInitializePort ( UINT32 Fractional; UINT32 HardwareFifoDepth; + HardwareFifoDepth = FixedPcdGet8 (PL011UartFifoDepth); +#if FixedPcdGet8 (PL011UartFifoDepth) == 0 HardwareFifoDepth = (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPID2)) \ > PL011_VER_R1P4) \ ? 32 : 16 ; +#endif + // The PL011 supports a buffer of 1, 16 or 32 chars. Therefore we can accept // 1 char buffer as the minimum FIFO size. Because everything can be rounded // down, there is no maximum FIFO size. diff --git a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf index d99e89f..3e5efc7 100644 --- a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf +++ b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf @@ -35,3 +35,4 @@ gArmPlatformTokenSpaceGuid.PL011UartInteger gArmPlatformTokenSpaceGuid.PL011UartFractional gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant + gArmPlatformTokenSpaceGuid.PL011UartFifoDepth -- 2.7.4