From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (NAM12-MW2-obe.outbound.protection.outlook.com [40.107.244.54]) by mx.groups.io with SMTP id smtpd.web11.75608.1674225131128031751 for ; Fri, 20 Jan 2023 06:32:11 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="body hash did not verify" header.i=@amd.com header.s=selector1 header.b=hdgZ4A7l; spf=permerror, err=parse error for token &{10 18 %{i}._ip.%{h}._ehlo.%{d}._spf.vali.email}: invalid domain name (domain: amd.com, ip: 40.107.244.54, mailfrom: abdullateef.attar@amd.com) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=DcoEu5ov8Zc7EUMbKyqkj6M4gakn8DMgq6Hl3x0+dFpnEGsVn5XOOHqVHAUIbSW+8zalD2OGRRvVC0thwlrCiEUmPC0lpr5nGgAoQjY6uFwOnpVfqqbLb+GYgwr6+uOvqXgUAPEAwh/kA1qzLcVAdQpwZB1nRnNkxloU8RNeRPrujN9U8ca5dsnRk4LIpLLbVYvi/+xPZihexUYlmK0/d9ClWFf/qHppE127mqOXGOxDgMocl0y7XqYeC2T3XNlnYHB9Qw+Y28f9d9gB+3zDTlKw7mFTXwJ67AiOeb9axk7/PFUtZYzJ6xAjGQ9f9UmKdfvnKKKHkYJvh4W2JyiR/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=msWDdxhvyL6I4fManKcVeJDaPEbJyqcLEkXz6/eNe0c=; b=PAf+qx4MQEA9EnEWI8ztzgwUfHVdZ3Y+HztOr1baBtpLRQNO6Yp6wf4tPZfRgCZmzAllNpyMAxhMyoOrKSq/qjtRawhRu2ijssONimyhtQR9M7u+Wsce3pPId054uSOqEp8ZrADoD98TIbIiFW39XQ4n0TGjDWOkBevwFPdrlyrd4lvpC1YoiKF+thNPCr00ELojasOT6SSS7uhlic5PIfmStwKbiK6aSuQ1flbPxDpLvW+rlXEwU/W20lkzJrrwDMHMPMNs0HJVxEa+uRK/OjaejDap8gHZ8TBm0707Rz3eiJ3wV5LcZ1L5rlagg/yMdKiSqjF6egJq9EMg05VrFg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=edk2.groups.io smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=msWDdxhvyL6I4fManKcVeJDaPEbJyqcLEkXz6/eNe0c=; b=hdgZ4A7lVeezS5o1VYBdBRE2d371SyTNzyCkxXtmM2r5sO22Om6sNUqNKQVzkr7OyLPAw5Uv5oWQPCVBFg1z28XpswcNfMzN13Hy8mtE1kcFzaZt1b1zkK2v9G5QXIynOM2zyusDzJ0dT6xWra9RuDbDxEhMNabp+0510DhMS/0= Received: from BN6PR17CA0026.namprd17.prod.outlook.com (2603:10b6:405:75::15) by BN9PR12MB5177.namprd12.prod.outlook.com (2603:10b6:408:11a::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.27; Fri, 20 Jan 2023 14:32:09 +0000 Received: from BN8NAM11FT101.eop-nam11.prod.protection.outlook.com (2603:10b6:405:75:cafe::a0) by BN6PR17CA0026.outlook.office365.com (2603:10b6:405:75::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6002.27 via Frontend Transport; Fri, 20 Jan 2023 14:32:09 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by BN8NAM11FT101.mail.protection.outlook.com (10.13.177.126) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6002.13 via Frontend Transport; Fri, 20 Jan 2023 14:32:09 +0000 Received: from SATLEXMB07.amd.com (10.181.41.45) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Fri, 20 Jan 2023 08:32:08 -0600 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB07.amd.com (10.181.41.45) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Fri, 20 Jan 2023 06:32:08 -0800 Received: from BLR-LAB-SFW01.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Fri, 20 Jan 2023 08:32:06 -0600 From: "Abdul Lateef Attar" To: CC: Abdul Lateef Attar , Paul Grimes , Garrett Kirkendall , Abner Chang , Eric Dong , Ray Ni , Rahul Kumar , Abdul Lateef Attar Subject: [PATCH v4 6/6] UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family Date: Fri, 20 Jan 2023 20:01:45 +0530 Message-ID: <5ce3292c895ce8c7d6fd9b59cb3aa55624a1288f.1674224845.git.abdattar@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Return-Path: AbdulLateef.Attar@amd.com X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT101:EE_|BN9PR12MB5177:EE_ X-MS-Office365-Filtering-Correlation-Id: 63b31e14-4dd8-46b8-e118-08dafaf31cb0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SDCn2YR5dEqH7bS82xZv0BbHBKn8y+9d6mI4KIL/Dp3zpy9SjQGm1iYd7QjVoyTv7t7vp/XbW3PFnN/bkgEHxZjo+xmpHHmL6pafJgLv5bYencNs+LC9DT4R7jY1Vsw4C09eq94SaraOB7MtwEqOI4HJfxlXOU9h+z37DA9emCMadOEPlx/HQCS4O5JyTT3/d5VdlutUHdTP2uRuhLWa5tbem3HP7+0sdkCTmYDvxsw2UudTusBwe+YWPzQXQuL48Vd31ZZKvsiNQoAkgk+pRpZIAqUFfmWH7oRkgGUmsf00t5tnUkJNqZ/dFsf52T6F7K5J12TUvmmSZktADMO9qHe9MMXVHRW+4tf3bDtbhM9jNgmT12L/7fwIAms/f8gcZrAemUEy9MJTSCWbH0nHINNtAgqqxY9rp3XZeXx2TCda5vLhpZ9LCYLyyX9Q0OnVrsKofluNL8vp/NMFY6j4rZYtFx7Jcblh5sBV0SLi5qJfYjXvS70o/R+03JcvfFP8eNjNEF/8GBe37Rpi7Flzojkk6tbYLiYzSzI7UuxluhzPpiGsK5skNBmFPiwYeMmPpaAUyp3On8xjAP9nVs86HLUy5S8ig0KHgbxeE12VeKiYosKaOGtLTyG5wDoKw+a/2644D3JvOdsfspWnOkaxIIso9j8WG1RNVWHbxT9V9+B8gzOp9wlo/K3EiFOmAAqyQuE7DmgL6jSa/QJi/1HvpCjiQK0Xu+2fuX5ZOz2Wp0fNlKI/5KSbbNQPqwha6lE5pLVgfeYEHbvnwjfPaVfIfg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(39860400002)(376002)(396003)(346002)(451199015)(36840700001)(46966006)(40470700004)(5660300002)(8936002)(4326008)(6916009)(8676002)(82310400005)(70586007)(70206006)(36860700001)(36756003)(6666004)(26005)(2906002)(186003)(54906003)(7696005)(966005)(478600001)(316002)(2616005)(83380400001)(41300700001)(356005)(40460700003)(82740400003)(40480700001)(81166007)(336012)(47076005)(426003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2023 14:32:09.1228 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 63b31e14-4dd8-46b8-e118-08dafaf31cb0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT101.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5177 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Abdul Lateef Attar BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4182 Implements interfaces to read and write save state registers of AMD's processor family. Initializes processor SMMADDR and MASK depends on PcdSmrrEnable flag. Program or corrects the IP once control returns from SMM. Cc: Paul Grimes Cc: Garrett Kirkendall Cc: Abner Chang Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Abdul Lateef Attar Reviewed-by: Abner Chang --- .../AmdSmmCpuFeaturesLib.inf | 6 + .../SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c | 106 +++++++++++++++++- 2 files changed, 109 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf = b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf index 4c77efc64462..9d5b8c2e972d 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf @@ -31,3 +31,9 @@ [LibraryClasses] PcdLib MemoryAllocationLib DebugLib + SmmSmramSaveStateLib + +[FeaturePcd] + gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable ## CONSUMES + diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c b/= UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c index c74e1a0c0c5b..af45be3e265a 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c @@ -11,6 +11,21 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =20 #include #include +#include +#include +#include +#include + +// EFER register LMA bit +#define LMA BIT10 + +// Machine Specific Registers (MSRs) +#define SMMADDR_ADDRESS 0xC0010112ul +#define SMMMASK_ADDRESS 0xC0010113ul +#define EFER_ADDRESS 0XC0000080ul + +// The mode of the CPU at the time an SMI occurs +STATIC UINT8 mSmmSaveStateRegisterLma; =20 /** Read an SMM Save State register on the target processor. If this functi= on @@ -39,7 +54,7 @@ SmmCpuFeaturesReadSaveStateRegister ( OUT VOID *Buffer ) { - return EFI_SUCCESS; + return SmramSaveStateReadRegister (CpuIndex, Register, Width, Buffer); } =20 /** @@ -67,7 +82,7 @@ SmmCpuFeaturesWriteSaveStateRegister ( IN CONST VOID *Buffer ) { - return EFI_SUCCESS; + return SmramSaveStateWriteRegister (CpuIndex, Register, Width, Buffer); } =20 /** @@ -82,6 +97,13 @@ CpuFeaturesLibInitialization ( VOID ) { + UINT32 LMAValue; + + LMAValue =3D (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA; + mSmmSaveStateRegisterLma =3D EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT; + if (LMAValue) { + mSmmSaveStateRegisterLma =3D EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; + } } =20 /** @@ -117,6 +139,52 @@ SmmCpuFeaturesInitializeProcessor ( IN CPU_HOT_PLUG_DATA *CpuHotPlugData ) { + AMD_SMRAM_SAVE_STATE_MAP *CpuState; + UINT32 LMAValue; + + // + // Configure SMBASE. + // + CpuState =3D (AMD_SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT= _SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); + CpuState->x64.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + + // Re-initialize the value of mSmmSaveStateRegisterLma flag which might = have been changed in PiCpuSmmDxeSmm Driver + // Entry point, to make sure correct value on AMD platform is assigned t= o be used by SmmCpuFeaturesLib. + LMAValue =3D (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA; + mSmmSaveStateRegisterLma =3D EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT; + if (LMAValue) { + mSmmSaveStateRegisterLma =3D EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; + } + + // + // If SMRR is supported, then program SMRR base/mask MSRs. + // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first norma= l SMI. + // The code that initializes SMM environment is running in normal mode + // from SMRAM region. If SMRR is enabled here, then the SMRAM region + // is protected and the normal mode code execution will fail. + // + if (FeaturePcdGet (PcdSmrrEnable)) { + // + // SMRR size cannot be less than 4-KBytes + // SMRR size must be of length 2^n + // SMRR base alignment cannot be less than SMRR length + // + if ((CpuHotPlugData->SmrrSize < SIZE_4KB) || + (CpuHotPlugData->SmrrSize !=3D GetPowerOfTwo32 (CpuHotPlugData->Sm= rrSize)) || + ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) !=3D= CpuHotPlugData->SmrrBase)) + { + // + // Print message and halt if CPU is Monarch + // + if (IsMonarch) { + DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet alignment/size r= equirement!\n")); + CpuDeadLoop (); + } + } else { + AsmWriteMsr64 (SMMADDR_ADDRESS, CpuHotPlugData->SmrrBase); + AsmWriteMsr64 (SMMMASK_ADDRESS, ((~(UINT64)(CpuHotPlugData->SmrrSize= - 1)) | 0x6600)); + } + } } =20 /** @@ -159,7 +227,39 @@ SmmCpuFeaturesHookReturnFromSmm ( IN UINT64 NewInstructionPointer ) { - return 0; + UINT64 OriginalInstructionPointer; + AMD_SMRAM_SAVE_STATE_MAP *AmdCpuState; + + AmdCpuState =3D (AMD_SMRAM_SAVE_STATE_MAP *)CpuState; + + if (mSmmSaveStateRegisterLma =3D=3D EFI_SMM_SAVE_STATE_REGISTER_LMA_32BI= T) { + OriginalInstructionPointer =3D (UINT64)AmdCpuState->x86._EIP; + AmdCpuState->x86._EIP =3D (UINT32)NewInstructionPointer; + // + // Clear the auto HALT restart flag so the RSM instruction returns + // program control to the instruction following the HLT instruction. + // + if ((AmdCpuState->x86.AutoHALTRestart & BIT0) !=3D 0) { + AmdCpuState->x86.AutoHALTRestart &=3D ~BIT0; + } + } else { + OriginalInstructionPointer =3D AmdCpuState->x64._RIP; + if ((AmdCpuState->x64.EFER & LMA) =3D=3D 0) { + AmdCpuState->x64._RIP =3D (UINT32)NewInstructionPointer32; + } else { + AmdCpuState->x64._RIP =3D (UINT32)NewInstructionPointer; + } + + // + // Clear the auto HALT restart flag so the RSM instruction returns + // program control to the instruction following the HLT instruction. + // + if ((AmdCpuState->x64.AutoHALTRestart & BIT0) !=3D 0) { + AmdCpuState->x64.AutoHALTRestart &=3D ~BIT0; + } + } + + return OriginalInstructionPointer; } =20 /** --=20 2.25.1