From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-1.mimecast.com (us-smtp-1.mimecast.com [207.211.31.120]) by mx.groups.io with SMTP id smtpd.web11.1891.1588791722586660481 for ; Wed, 06 May 2020 12:02:02 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=aA/CWytS; spf=pass (domain: redhat.com, ip: 207.211.31.120, mailfrom: lersek@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1588791721; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1pigtWya7hvTg2QRBBATBvxMJArLeJdoZOyYuOgv/fs=; b=aA/CWytSzdQrbHxye0SHo/E5ZEkrwiC0WpMUUKmSweUJ22XucQc674pBiVR5WNxv/vZt1u 6eg/11/lR+BsOL1dwpupRg28sMNY0lA0okeNmXnCbpbLxG4Y+KDXC0/pyHTBwzj9Wdpa45 EAd8pVkNLEWhcIp8qbdD4ZosBcho7UY= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-297-0DdbLJw4P2ar2_D6-PFo8A-1; Wed, 06 May 2020 15:01:51 -0400 X-MC-Unique: 0DdbLJw4P2ar2_D6-PFo8A-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id AE4831895A29; Wed, 6 May 2020 19:01:44 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-112-227.ams2.redhat.com [10.36.112.227]) by smtp.corp.redhat.com (Postfix) with ESMTP id E1A505F7E2; Wed, 6 May 2020 19:01:41 +0000 (UTC) Subject: Re: [PATCH v2 1/3] UefiCpuPkg/CpuExceptionHandler: Make XCODE5 changes toolchain specific To: Tom Lendacky , devel@edk2.groups.io Cc: Jordan Justen , Ard Biesheuvel , Liming Gao , Eric Dong , Ray Ni , Anthony Perard , Julien Grall , Brijesh Singh , Andrew Fish References: <5fad89a0bdea4743b13815078e68bcf122c4f63b.1588782781.git.thomas.lendacky@amd.com> From: "Laszlo Ersek" Message-ID: <5d973f64-22fa-6f83-7b1b-cb97a7efe400@redhat.com> Date: Wed, 6 May 2020 21:01:40 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <5fad89a0bdea4743b13815078e68bcf122c4f63b.1588782781.git.thomas.lendacky@amd.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit On 05/06/20 18:33, Tom Lendacky wrote: > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2340 > > Commit 2db0ccc2d7fe ("UefiCpuPkg: Update CpuExceptionHandlerLib pass > XCODE5 tool chain") introduced binary patching into the exception handling > support. CPU exception handling is allowed during SEC and this results in > binary patching of flash, which should not be done. > > Separate the changes from commit 2db0ccc2d7fe into an XCODE5 toolchain > specific file, Xcode5ExceptionHandlerAsm.nasm, and create a new SEC INF > file for the XCODE5 version of CpuExceptionHandlerLib. > > Since binary patching is allowed when running outside of flash, switch > the Dxe, Pei and Smm versions of the CpuExceptionHandlerLib over to use > the Xcode5ExceptionHandlerAsm.nasm file to retain current functionality. > > Cc: Eric Dong > Cc: Ray Ni > Cc: Laszlo Ersek > Cc: Liming Gao > Signed-off-by: Tom Lendacky > --- > UefiCpuPkg/UefiCpuPkg.dsc | 5 + > .../DxeCpuExceptionHandlerLib.inf | 2 +- > .../PeiCpuExceptionHandlerLib.inf | 2 +- > .../SmmCpuExceptionHandlerLib.inf | 2 +- > .../Xcode5SecPeiCpuExceptionHandlerLib.inf | 54 +++ > .../X64/Xcode5ExceptionHandlerAsm.nasm | 396 ++++++++++++++++++ > .../Xcode5SecPeiCpuExceptionHandlerLib.uni | 17 + > 7 files changed, 475 insertions(+), 3 deletions(-) > create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.inf > create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm > create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.uni > > diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc > index d28cb5cccb52..264e5a787bce 100644 > --- a/UefiCpuPkg/UefiCpuPkg.dsc > +++ b/UefiCpuPkg/UefiCpuPkg.dsc > @@ -59,7 +59,11 @@ [LibraryClasses] > > [LibraryClasses.common.SEC] > PlatformSecLib|UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.inf > +!if $(TOOL_CHAIN_TAG) == "XCODE5" > + CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.inf > +!else > CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf > +!endif > HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf > PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf > MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf > @@ -126,6 +130,7 @@ [Components.IA32, Components.X64] > UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf (1) I think this lib instance ("SecPeiCpuExceptionHandlerLib.inf") may not build with XCODE5 at the end of the series, even in stand-alone mode. Thus I think it should be conditionalized with !if $(TOOL_CHAIN_TAG) != "XCODE5" ... !endif When using XCODE5, we should only build "Xcode5SecPeiCpuExceptionHandlerLib.inf"; otherwise, we should build *both* "SecPeiCpuExceptionHandlerLib.inf" and "Xcode5SecPeiCpuExceptionHandlerLib.inf". > UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf > UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf > + UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.inf > UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf > UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf > UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.inf > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf > index e41383573043..61e2ec30b089 100644 > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf > @@ -28,7 +28,7 @@ [Sources.Ia32] > Ia32/ArchInterruptDefs.h > > [Sources.X64] > - X64/ExceptionHandlerAsm.nasm > + X64/Xcode5ExceptionHandlerAsm.nasm > X64/ArchExceptionHandler.c > X64/ArchInterruptDefs.h > > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf > index f31423ac0f91..093374944df6 100644 > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf > @@ -28,7 +28,7 @@ [Sources.Ia32] > Ia32/ArchInterruptDefs.h > > [Sources.X64] > - X64/ExceptionHandlerAsm.nasm > + X64/Xcode5ExceptionHandlerAsm.nasm > X64/ArchExceptionHandler.c > X64/ArchInterruptDefs.h > > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf > index 66c7f59e3c91..2ffbbccc302f 100644 > --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf > @@ -28,7 +28,7 @@ [Sources.Ia32] > Ia32/ArchInterruptDefs.h > > [Sources.X64] > - X64/ExceptionHandlerAsm.nasm > + X64/Xcode5ExceptionHandlerAsm.nasm > X64/ArchExceptionHandler.c > X64/ArchInterruptDefs.h > > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.inf > new file mode 100644 > index 000000000000..3ed1378d6fa6 > --- /dev/null > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.inf > @@ -0,0 +1,54 @@ > +## @file > +# CPU Exception Handler library instance for SEC/PEI modules. > +# > +# Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent (2) This is a customized copy of "SecPeiCpuExceptionHandlerLib.inf"; I think you should prepend your (C) notice. > +# > +# This is the XCODE5 variant of the SEC/PEI CpuExceptionHandlerLib. This > +# variant performs binary patching to fix up addresses that allow the > +# XCODE5 toolchain to be used. > +# > +## > + > +[Defines] > + INF_VERSION = 0x00010005 > + BASE_NAME = Xcode5SecPeiCpuExceptionHandlerLib > + MODULE_UNI_FILE = Xcode5SecPeiCpuExceptionHandlerLib.uni > + FILE_GUID = 49C481AF-1621-42F3-8FA1-27C64143E304 > + MODULE_TYPE = PEIM > + VERSION_STRING = 1.1 > + LIBRARY_CLASS = CpuExceptionHandlerLib|SEC PEI_CORE PEIM > + > +# > +# The following information is for reference only and not required by the build tools. > +# > +# VALID_ARCHITECTURES = IA32 X64 > +# > + > +[Sources.Ia32] > + Ia32/ExceptionHandlerAsm.nasm > + Ia32/ExceptionTssEntryAsm.nasm > + Ia32/ArchExceptionHandler.c > + Ia32/ArchInterruptDefs.h > + > +[Sources.X64] > + X64/Xcode5ExceptionHandlerAsm.nasm > + X64/ArchExceptionHandler.c > + X64/ArchInterruptDefs.h > + > +[Sources.common] > + CpuExceptionCommon.h > + CpuExceptionCommon.c > + SecPeiCpuException.c > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + UefiCpuPkg/UefiCpuPkg.dec > + > +[LibraryClasses] > + BaseLib > + SerialPortLib > + PrintLib > + LocalApicLib > + PeCoffGetEntryPointLib > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm > new file mode 100644 > index 000000000000..19198f273137 > --- /dev/null > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerAsm.nasm > @@ -0,0 +1,396 @@ > +;------------------------------------------------------------------------------ ; > +; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
> +; SPDX-License-Identifier: BSD-2-Clause-Patent This is identical to "ExceptionHandlerAsm.nasm", so I agree a new (C) notice is not needed. > +; > +; Module Name: > +; > +; ExceptionHandlerAsm.Asm > +; > +; Abstract: > +; > +; x64 CPU Exception Handler > +; > +; Notes: > +; > +;------------------------------------------------------------------------------ > + > +; > +; CommonExceptionHandler() > +; > + > +extern ASM_PFX(mErrorCodeFlag) ; Error code flags for exceptions > +extern ASM_PFX(mDoFarReturnFlag) ; Do far return flag > +extern ASM_PFX(CommonExceptionHandler) > + > +SECTION .data > + > +DEFAULT REL > +SECTION .text > + > +ALIGN 8 > + > +AsmIdtVectorBegin: > +%rep 32 > + db 0x6a ; push #VectorNum > + db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum > + push rax > + mov rax, strict qword 0 ; mov rax, ASM_PFX(CommonInterruptEntry) > + jmp rax > +%endrep > +AsmIdtVectorEnd: > + > +HookAfterStubHeaderBegin: > + db 0x6a ; push > +@VectorNum: > + db 0 ; 0 will be fixed > + push rax > + mov rax, strict qword 0 ; mov rax, HookAfterStubHeaderEnd > +JmpAbsoluteAddress: > + jmp rax > +HookAfterStubHeaderEnd: > + mov rax, rsp > + and sp, 0xfff0 ; make sure 16-byte aligned for exception context > + sub rsp, 0x18 ; reserve room for filling exception data later > + push rcx > + mov rcx, [rax + 8] > + bt [ASM_PFX(mErrorCodeFlag)], ecx > + jnc .0 > + push qword [rsp] ; push additional rcx to make stack alignment > +.0: > + xchg rcx, [rsp] ; restore rcx, save Exception Number in stack > + push qword [rax] ; push rax into stack to keep code consistence > + > +;---------------------------------------; > +; CommonInterruptEntry ; > +;---------------------------------------; > +; The follow algorithm is used for the common interrupt routine. > +; Entry from each interrupt with a push eax and eax=interrupt number > +; Stack frame would be as follows as specified in IA32 manuals: > +; > +; +---------------------+ <-- 16-byte aligned ensured by processor > +; + Old SS + > +; +---------------------+ > +; + Old RSP + > +; +---------------------+ > +; + RFlags + > +; +---------------------+ > +; + CS + > +; +---------------------+ > +; + RIP + > +; +---------------------+ > +; + Error Code + > +; +---------------------+ > +; + Vector Number + > +; +---------------------+ > +; + RBP + > +; +---------------------+ <-- RBP, 16-byte aligned > +; The follow algorithm is used for the common interrupt routine. > +global ASM_PFX(CommonInterruptEntry) > +ASM_PFX(CommonInterruptEntry): > + cli > + pop rax > + ; > + ; All interrupt handlers are invoked through interrupt gates, so > + ; IF flag automatically cleared at the entry point > + ; > + xchg rcx, [rsp] ; Save rcx into stack and save vector number into rcx > + and rcx, 0xFF > + cmp ecx, 32 ; Intel reserved vector for exceptions? > + jae NoErrorCode > + bt [ASM_PFX(mErrorCodeFlag)], ecx > + jc HasErrorCode > + > +NoErrorCode: > + > + ; > + ; Push a dummy error code on the stack > + ; to maintain coherent stack map > + ; > + push qword [rsp] > + mov qword [rsp + 8], 0 > +HasErrorCode: > + push rbp > + mov rbp, rsp > + push 0 ; clear EXCEPTION_HANDLER_CONTEXT.OldIdtHandler > + push 0 ; clear EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag > + > + ; > + ; Stack: > + ; +---------------------+ <-- 16-byte aligned ensured by processor > + ; + Old SS + > + ; +---------------------+ > + ; + Old RSP + > + ; +---------------------+ > + ; + RFlags + > + ; +---------------------+ > + ; + CS + > + ; +---------------------+ > + ; + RIP + > + ; +---------------------+ > + ; + Error Code + > + ; +---------------------+ > + ; + RCX / Vector Number + > + ; +---------------------+ > + ; + RBP + > + ; +---------------------+ <-- RBP, 16-byte aligned > + ; > + > + ; > + ; Since here the stack pointer is 16-byte aligned, so > + ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64 > + ; is 16-byte aligned > + ; > + > +;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax; > +;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15; > + push r15 > + push r14 > + push r13 > + push r12 > + push r11 > + push r10 > + push r9 > + push r8 > + push rax > + push qword [rbp + 8] ; RCX > + push rdx > + push rbx > + push qword [rbp + 48] ; RSP > + push qword [rbp] ; RBP > + push rsi > + push rdi > + > +;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero > + movzx rax, word [rbp + 56] > + push rax ; for ss > + movzx rax, word [rbp + 32] > + push rax ; for cs > + mov rax, ds > + push rax > + mov rax, es > + push rax > + mov rax, fs > + push rax > + mov rax, gs > + push rax > + > + mov [rbp + 8], rcx ; save vector number > + > +;; UINT64 Rip; > + push qword [rbp + 24] > + > +;; UINT64 Gdtr[2], Idtr[2]; > + xor rax, rax > + push rax > + push rax > + sidt [rsp] > + mov bx, word [rsp] > + mov rax, qword [rsp + 2] > + mov qword [rsp], rax > + mov word [rsp + 8], bx > + > + xor rax, rax > + push rax > + push rax > + sgdt [rsp] > + mov bx, word [rsp] > + mov rax, qword [rsp + 2] > + mov qword [rsp], rax > + mov word [rsp + 8], bx > + > +;; UINT64 Ldtr, Tr; > + xor rax, rax > + str ax > + push rax > + sldt ax > + push rax > + > +;; UINT64 RFlags; > + push qword [rbp + 40] > + > +;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8; > + mov rax, cr8 > + push rax > + mov rax, cr4 > + or rax, 0x208 > + mov cr4, rax > + push rax > + mov rax, cr3 > + push rax > + mov rax, cr2 > + push rax > + xor rax, rax > + push rax > + mov rax, cr0 > + push rax > + > +;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; > + mov rax, dr7 > + push rax > + mov rax, dr6 > + push rax > + mov rax, dr3 > + push rax > + mov rax, dr2 > + push rax > + mov rax, dr1 > + push rax > + mov rax, dr0 > + push rax > + > +;; FX_SAVE_STATE_X64 FxSaveState; > + sub rsp, 512 > + mov rdi, rsp > + db 0xf, 0xae, 0x7 ;fxsave [rdi] > + > +;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear > + cld > + > +;; UINT32 ExceptionData; > + push qword [rbp + 16] > + > +;; Prepare parameter and call > + mov rcx, [rbp + 8] > + mov rdx, rsp > + ; > + ; Per X64 calling convention, allocate maximum parameter stack space > + ; and make sure RSP is 16-byte aligned > + ; > + sub rsp, 4 * 8 + 8 > + call ASM_PFX(CommonExceptionHandler) > + add rsp, 4 * 8 + 8 > + > + cli > +;; UINT64 ExceptionData; > + add rsp, 8 > + > +;; FX_SAVE_STATE_X64 FxSaveState; > + > + mov rsi, rsp > + db 0xf, 0xae, 0xE ; fxrstor [rsi] > + add rsp, 512 > + > +;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; > +;; Skip restoration of DRx registers to support in-circuit emualators > +;; or debuggers set breakpoint in interrupt/exception context > + add rsp, 8 * 6 > + > +;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8; > + pop rax > + mov cr0, rax > + add rsp, 8 ; not for Cr1 > + pop rax > + mov cr2, rax > + pop rax > + mov cr3, rax > + pop rax > + mov cr4, rax > + pop rax > + mov cr8, rax > + > +;; UINT64 RFlags; > + pop qword [rbp + 40] > + > +;; UINT64 Ldtr, Tr; > +;; UINT64 Gdtr[2], Idtr[2]; > +;; Best not let anyone mess with these particular registers... > + add rsp, 48 > + > +;; UINT64 Rip; > + pop qword [rbp + 24] > + > +;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; > + pop rax > + ; mov gs, rax ; not for gs > + pop rax > + ; mov fs, rax ; not for fs > + ; (X64 will not use fs and gs, so we do not restore it) > + pop rax > + mov es, rax > + pop rax > + mov ds, rax > + pop qword [rbp + 32] ; for cs > + pop qword [rbp + 56] ; for ss > + > +;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax; > +;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15; > + pop rdi > + pop rsi > + add rsp, 8 ; not for rbp > + pop qword [rbp + 48] ; for rsp > + pop rbx > + pop rdx > + pop rcx > + pop rax > + pop r8 > + pop r9 > + pop r10 > + pop r11 > + pop r12 > + pop r13 > + pop r14 > + pop r15 > + > + mov rsp, rbp > + pop rbp > + add rsp, 16 > + cmp qword [rsp - 32], 0 ; check EXCEPTION_HANDLER_CONTEXT.OldIdtHandler > + jz DoReturn > + cmp qword [rsp - 40], 1 ; check EXCEPTION_HANDLER_CONTEXT.ExceptionDataFlag > + jz ErrorCode > + jmp qword [rsp - 32] > +ErrorCode: > + sub rsp, 8 > + jmp qword [rsp - 24] > + > +DoReturn: > + cmp qword [ASM_PFX(mDoFarReturnFlag)], 0 ; Check if need to do far return instead of IRET > + jz DoIret > + push rax > + mov rax, rsp ; save old RSP to rax > + mov rsp, [rsp + 0x20] > + push qword [rax + 0x10] ; save CS in new location > + push qword [rax + 0x8] ; save EIP in new location > + push qword [rax + 0x18] ; save EFLAGS in new location > + mov rax, [rax] ; restore rax > + popfq ; restore EFLAGS > + DB 0x48 ; prefix to composite "retq" with next "retf" > + retf ; far return > +DoIret: > + iretq > + > +;------------------------------------------------------------------------------------- > +; GetTemplateAddressMap (&AddressMap); > +;------------------------------------------------------------------------------------- > +; comments here for definition of address map > +global ASM_PFX(AsmGetTemplateAddressMap) > +ASM_PFX(AsmGetTemplateAddressMap): > + lea rax, [AsmIdtVectorBegin] > + mov qword [rcx], rax > + mov qword [rcx + 0x8], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32 > + lea rax, [HookAfterStubHeaderBegin] > + mov qword [rcx + 0x10], rax > + > +; Fix up CommonInterruptEntry address > + lea rax, [ASM_PFX(CommonInterruptEntry)] > + lea rcx, [AsmIdtVectorBegin] > +%rep 32 > + mov qword [rcx + (JmpAbsoluteAddress - 8 - HookAfterStubHeaderBegin)], rax > + add rcx, (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32 > +%endrep > +; Fix up HookAfterStubHeaderEnd > + lea rax, [HookAfterStubHeaderEnd] > + lea rcx, [JmpAbsoluteAddress] > + mov qword [rcx - 8], rax > + > + ret > + > +;------------------------------------------------------------------------------------- > +; AsmVectorNumFixup (*NewVectorAddr, VectorNum, *OldVectorAddr); > +;------------------------------------------------------------------------------------- > +global ASM_PFX(AsmVectorNumFixup) > +ASM_PFX(AsmVectorNumFixup): > + mov rax, rdx > + mov [rcx + (@VectorNum - HookAfterStubHeaderBegin)], al > + ret > + > diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.uni b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.uni > new file mode 100644 > index 000000000000..be69992cef09 > --- /dev/null > +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.uni > @@ -0,0 +1,17 @@ > +// /** @file > +// XCODE5 CPU Exception Handler library instance for SEC/PEI modules. > +// > +// CPU Exception Handler library instance for SEC/PEI modules when built > +// using the XCODE5 toolchain. > +// > +// Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.
> +// > +// SPDX-License-Identifier: BSD-2-Clause-Patent > +// > +// **/ > + > + > +#string STR_MODULE_ABSTRACT #language en-US "CPU Exception Handler library instance for SEC/PEI modules with the XCODE5 toolchain." > + > +#string STR_MODULE_DESCRIPTION #language en-US "CPU Exception Handler library instance for SEC/PEI modules with the XCODE5 toolchain." > + > (3) This is a brand new file; I think you should prepend your (C) notice. Meta-hint: with patches like this, it sometimes makes sense to format the series for posting with "--find-copies-harder". With (1) through (3) updated: Reviewed-by: Laszlo Ersek Thanks, Laszlo