From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from hqnvemgate25.nvidia.com (hqnvemgate25.nvidia.com [216.228.121.64]) by mx.groups.io with SMTP id smtpd.web10.12793.1580147568626259916 for ; Mon, 27 Jan 2020 09:52:48 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@nvidia.com header.s=n1 header.b=epxlJap0; spf=pass (domain: nvidia.com, ip: 216.228.121.64, mailfrom: ashishsingha@nvidia.com) Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 27 Jan 2020 09:52:29 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 27 Jan 2020 09:52:48 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 27 Jan 2020 09:52:48 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 27 Jan 2020 17:52:48 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 27 Jan 2020 17:52:47 +0000 Received: from ashishsingha-lnx.nvidia.com (Not Verified[10.28.48.147]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 27 Jan 2020 09:52:47 -0800 From: "Ashish Singhal" To: , , , , CC: Ashish Singhal Subject: [PATCH] MdeModulePkg/BaseSerialPortLib16550: Fix Serial Port Ready Date: Mon, 27 Jan 2020 10:52:45 -0700 Message-ID: <5d9ffe00de052a95ac04319951d7466644cf78c1.1580147315.git.ashishsingha@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public Return-Path: ashishsingha@nvidia.com MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1580147549; bh=uMaI2Jurouv26eI+PDFQC/Q4WlRnKUbsns6UT7lKEJk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=epxlJap0XMYPgM8w4JZvsFa+8m5rIINH9U0OLZRAAgWpEhT7XemDQyoecyzewiEmw DgMPUykgD1U22+JSN1crUGHb6HcSBX4qQOxFElNwDXglbo0WZOvxlHgQq4c+/omcMm nT8xJUbk8JiorfK2Q3VItVjci84so1WTE7pEOYZsSL158e7xIDlVyTW/lR/pWTmaOG ZiJbi4HaCyZybxbfGxbfoI2cTkrynjfnw24dvZllTnVTZoe8U+eB8X7GBIApjTSshR Udbr9eC1uUKeX8dzA9CZ4qFj/M/7dFAmngfKoToHZx86gexp0b4lcEVviqTRBLrJwY xgZeGkDeH1ZBA== Content-Type: text/plain Before writing data to FIFO, wait for the serial port to be ready, to make sure both the transmit FIFO and shift register empty. Code comment was saying the right thing but code was missing a check. Signed-off-by: Ashish Singhal --- .../Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c index bbae379887..9cb50dd80d 100644 --- a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c +++ b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c @@ -646,7 +646,7 @@ SerialPortWrite ( // Wait for the serial port to be ready, to make sure both the transmit FIFO // and shift register empty. // - while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_TEMT) == 0); + while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)); // // Fill then entire Tx FIFO -- 2.17.1