From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 7EA817803E1 for ; Thu, 15 Feb 2024 17:00:56 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=p+eAovrwqcbjv9zigpgwA5Oa90+SgK8mHN2qE373l7A=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1708016455; v=1; b=niKsl2GM8ylq4kkQ+P2Fd0BBV1FDNEwJuaRdvUdheDRBOqPzVZEG+rja7f45GtNXw99ihtg0 f4fGeKKHJkd6QYReLTdjaX639E/dnC4OEW8Y+G8fIS4XPIs7KUCDW1OIzJonFQ4KGAaggDUHlzx zytIoMQiYZ2xZepKUf5Vub+o= X-Received: by 127.0.0.2 with SMTP id Ks0MYY7687511xPX2XXHwzIF; Thu, 15 Feb 2024 09:00:55 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) by mx.groups.io with SMTP id smtpd.web11.19392.1708016453982264680 for ; Thu, 15 Feb 2024 09:00:54 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10985"; a="12665053" X-IronPort-AV: E=Sophos;i="6.06,162,1705392000"; d="scan'208";a="12665053" X-Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2024 09:00:54 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,162,1705392000"; d="scan'208";a="3977840" X-Received: from cbduggap-mobl.gar.corp.intel.com ([10.215.183.190]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2024 09:00:52 -0800 From: "cbduggap" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone , Chiu Chasel Subject: [edk2-devel] [PATCH] IntelFsp2Pkg: Fsp 2.x Changes Date: Thu, 15 Feb 2024 22:30:29 +0530 Message-Id: <5eaf18659418af4ccc5afbebe43f086da86b1695.1708016411.git.chinni.b.duggapu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chinni.b.duggapu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: aH7XnQQ04CZk8aLtdB8uRTvZx7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=niKsl2GM; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Changes to support spec changes 1. Remove usage of Pcd. 2. Change code to validate the Temporary Ram size input. 3. Consume the input saved in YMM Register Cc: Sai Chaganty Cc: Nate DeSimone Cc: Chiu Chasel Signed-off-by: cbduggap --- .../FspSecCore/Ia32/Fsp24ApiEntryM.nasm | 1 - .../FspSecCore/Ia32/FspApiEntryM.nasm | 1 - .../FspSecCore/Ia32/FspApiEntryT.nasm | 110 ++++++++++++------ .../FspSecCore/Ia32/SaveRestoreSseNasm.inc | 11 ++ IntelFsp2Pkg/FspSecCore/SecFsp.c | 1 - IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 4 +- IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 69 +++++++++-- IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm | 6 +- IntelFsp2Pkg/Include/FspEas/FspApi.h | 5 +- .../Include/SaveRestoreSseAvxNasm.inc | 21 ++++ .../SecRamInitData.c | 3 +- 11 files changed, 175 insertions(+), 57 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm b/IntelFsp2Pk= g/FspSecCore/Ia32/Fsp24ApiEntryM.nasm index 15f8ecea83..5fa5c03569 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm @@ -11,7 +11,6 @@ ; Following are fixed PCDs=0D ;=0D extern ASM_PFX(PcdGet32(PcdTemporaryRamBase))=0D -extern ASM_PFX(PcdGet32(PcdTemporaryRamSize))=0D extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))=0D extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))=0D =0D diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryM.nasm index 61ab4612a3..861cce4d01 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm @@ -11,7 +11,6 @@ ; Following are fixed PCDs=0D ;=0D extern ASM_PFX(PcdGet32(PcdTemporaryRamBase))=0D -extern ASM_PFX(PcdGet32(PcdTemporaryRamSize))=0D extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))=0D extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))=0D =0D diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryT.nasm index 900126b93b..5fca46ca7a 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -109,7 +109,8 @@ struc LoadMicrocodeParamsFsp24 .FsptArchReserved: resb 3=0D .FsptArchLength: resd 1=0D .FspDebugHandler resq 1=0D - .FsptArchUpd: resd 4=0D + .FspTemporaryRamSize: resd 1 ; Supported only if ArchRevison i= s >=3D 3=0D + .FsptArchUpd: resd 3=0D ; }=0D ; FSPT_CORE_UPD {=0D .MicrocodeCodeAddr: resq 1=0D @@ -178,29 +179,6 @@ endstruc jmp ebp ; restore EIP from EBP=0D %endmacro=0D =0D -;=0D -; Load UPD region pointer in ECX=0D -;=0D -global ASM_PFX(LoadUpdPointerToECX)=0D -ASM_PFX(LoadUpdPointerToECX):=0D - ;=0D - ; esp + 4 is input UPD parameter=0D - ; If esp + 4 is NULL the default UPD should be used=0D - ; ecx will be the UPD region that should be used=0D - ;=0D - mov ecx, dword [esp + 4]=0D - cmp ecx, 0=0D - jnz ParamValid=0D -=0D - ;=0D - ; Fall back to default UPD region=0D - ;=0D - CALL_EDI ASM_PFX(AsmGetFspInfoHeaderNoStack)=0D - mov ecx, DWORD [eax + 01Ch] ; Read FsptImageBaseAddress=0D - add ecx, DWORD [eax + 024h] ; Get Cfg Region base address =3D= FsptImageBaseAddress + CfgRegionOffset=0D -ParamValid:=0D - RET_EBP=0D -=0D ;=0D ; @todo: The strong/weak implementation does not work.=0D ; This needs to be reviewed later.=0D @@ -267,7 +245,7 @@ ASM_PFX(LoadMicrocodeDefault): cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2=0D jb Fsp20UpdHeader=0D cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2=0D - je Fsp24UpdHeader=0D + jae Fsp24UpdHeader=0D jmp Fsp22UpdHeader=0D =0D Fsp20UpdHeader:=0D @@ -405,7 +383,7 @@ CheckAddress: cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2=0D jb Fsp20UpdHeader1=0D cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2=0D - je Fsp24UpdHeader1;=0D + jae Fsp24UpdHeader1;=0D jmp Fsp22UpdHeader1=0D =0D Fsp20UpdHeader1:=0D @@ -497,7 +475,8 @@ ASM_PFX(EstablishStackFsp): ; Enable FSP STACK=0D ;=0D mov esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]=0D - add esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]=0D + LOAD_TEMPORARY_RAM_SIZE eax=0D + add esp, eax=0D =0D push DATA_LEN_OF_MCUD ; Size of the data region=0D push 4455434Dh ; Signature of the data region 'MCUD'=0D @@ -506,7 +485,7 @@ ASM_PFX(EstablishStackFsp): cmp byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2= =0D jb Fsp20UpdHeader2=0D cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2=0D - je Fsp24UpdHeader2=0D + jae Fsp24UpdHeader2=0D jmp Fsp22UpdHeader2=0D =0D Fsp20UpdHeader2:=0D @@ -554,12 +533,13 @@ ContinueAfterUpdPush: ;=0D ; Set ECX/EDX to the BootLoader temporary memory range=0D ;=0D - mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]=0D - mov edx, ecx=0D - add edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]=0D + mov edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]=0D + LOAD_TEMPORARY_RAM_SIZE ecx=0D + add edx, ecx=0D sub edx, [ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))]=0D + mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]=0D =0D - cmp ecx, edx ;If PcdFspReservedBufferSize >=3D PcdTemporary= RamSize, then error.=0D + cmp ecx, edx ;If PcdFspReservedBufferSize >=3D TemporaryRam= Size, then error.=0D jb EstablishStackFspSuccess=0D mov eax, 80000003h ;EFI_UNSUPPORTED=0D jmp EstablishStackFspExit=0D @@ -589,6 +569,30 @@ ASM_PFX(TempRamInitApi): ;=0D SAVE_REGS=0D =0D + ;=0D + ;=0D + ; Read Fsp Info header and save in esi=0D + ;=0D + CALL_EDI ASM_PFX(AsmGetFspInfoHeaderNoStack)=0D + xor esi, esi=0D + mov esi, eax=0D + ;=0D + ; esp + 4 is input UPD parameter=0D + ; If esp + 4 is NULL the default UPD should be used=0D + ; ecx will be the UPD region that should be used=0D + ;=0D + mov ecx, dword [esp + 4]=0D + cmp ecx, 0=0D + jnz ParamValid=0D +=0D + ;=0D + ; Fall back to default UPD region=0D + ;=0D + xor ecx, ecx=0D + mov ecx, DWORD [esi + 01Ch] ; Read FsptImageBaseAddress=0D + add ecx, DWORD [esi + 024h] ; Get Cfg Region base address =3D= FsptImageBaseAddress + CfgRegionOffset=0D +ParamValid:=0D + SAVE_ECX=0D ;=0D ; Save timestamp into XMM6=0D ;=0D @@ -596,9 +600,47 @@ ASM_PFX(TempRamInitApi): SAVE_EAX=0D SAVE_EDX=0D =0D - CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param=0D - SAVE_ECX ; save UPD param to slot 3 in xmm= 6=0D + mov edx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize))=0D + mov edx, DWORD [edx]=0D + ;=0D + ; Read ARCH2 UPD input value.=0D + ;=0D + mov ebx, DWORD [ecx + LoadMicrocodeParamsFsp24.FspTemporaryRamSize= ]=0D + ;=0D + ; As per spec, if Bootloader pass zero, use Fsp defined Size=0D + ; Irrespective of whether this UPD is supported or not, Fallback=0D + ; to Fsp defined size if input is zero.=0D + ;=0D + cmp ebx, 0=0D + jz UseTemporaryRamSizePcd=0D =0D + xor eax, eax=0D + mov ax, WORD [esi + 020h] ; Read ImageAttribute=0D + test ax, 16 ; check if Bit4 is set=0D + jnz ConsumeInputConfiguration=0D + ;=0D + ; Sometimes user may change input value even if it is not supported=0D + ; return error if input is Non-Zero and not same as PcdTemporaryRamSize.= =0D + ;=0D + cmp ebx, edx=0D + je UseTemporaryRamSizePcd=0D + mov eax, 080000002h ; RETURN_INVALID_PARAMETER=0D + jmp TempRamInitExit=0D +ConsumeInputConfiguration:=0D + ;=0D + ; Read Fsp Arch2 revision=0D + ;=0D + cmp byte [ecx + LoadMicrocodeParamsFsp24.FsptArchRevision], 3=0D + jb UseTemporaryRamSizePcd=0D + ;=0D + ; Read ARCH2 UPD value and Save.=0D + ;=0D + SAVE_TEMPORARY_RAM_SIZE ebx=0D + jmp GotTemporaryRamSize=0D +UseTemporaryRamSizePcd:=0D + SAVE_TEMPORARY_RAM_SIZE edx=0D +GotTemporaryRamSize:=0D + LOAD_ECX=0D ;=0D ; Sec Platform Init=0D ;=0D diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFsp= 2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc index 016f943b43..4d6ec1e984 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc @@ -128,6 +128,17 @@ SXMMN xmm5, 1, eax=0D %endmacro=0D =0D +;=0D +; XMM5 slot 2 for TemporaryRamSize=0D +;=0D +%macro LOAD_TEMPORARY_RAM_SIZE 1=0D + LXMMN xmm5, %1, 2=0D + %endmacro=0D +=0D +%macro SAVE_TEMPORARY_RAM_SIZE 1=0D + SXMMN xmm5, 2, %1=0D + %endmacro=0D +=0D %macro ENABLE_SSE 0=0D ;=0D ; Initialize floating point units=0D diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/Sec= Fsp.c index 11be1f97ca..4d519f726a 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c @@ -147,7 +147,6 @@ FspGlobalDataInit ( // It may have multiple FVs, so look into the last one for FSP header=0D //=0D PeiFspData->FspInfoHeader =3D (FSP_INFO_HEADER *)(UINTN)AsmGetFspInfoHea= der ();=0D - SecGetPlatformData (PeiFspData);=0D =0D //=0D // Set API calling mode=0D diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c b/IntelFsp2Pkg/FspSecCo= re/SecFspApiChk.c index 5f59938518..33aaac66c1 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c @@ -42,9 +42,7 @@ FspApiCallingCheck ( //=0D // FspMemoryInit check=0D //=0D - if (((UINTN)FspData !=3D MAX_ADDRESS) && ((UINTN)FspData !=3D MAX_UINT= 32)) {=0D - Status =3D EFI_UNSUPPORTED;=0D - } else if (ApiParam =3D=3D NULL) {=0D + if (ApiParam =3D=3D NULL) {=0D Status =3D EFI_SUCCESS;=0D } else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) {=0D Status =3D EFI_INVALID_PARAMETER;=0D diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/F= spSecCore/X64/FspApiEntryT.nasm index 698bb063a7..feb8164134 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -76,7 +76,8 @@ struc LoadMicrocodeParamsFsp24 .FsptArchReserved: resb 3=0D .FsptArchLength: resd 1=0D .FspDebugHandler resq 1=0D - .FsptArchUpd: resd 4=0D + .FspTemporaryRamSize: resd 1 ; Supported only if ArchRevison is= >=3D 3=0D + .FsptArchUpd: resd 3=0D ; }=0D ; FSPT_CORE_UPD {=0D .MicrocodeCodeAddr: resq 1=0D @@ -163,7 +164,7 @@ ASM_PFX(LoadMicrocodeDefault): cmp byte [rsp + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2=0D jb ParamError=0D cmp byte [rsp + LoadMicrocodeParamsFsp24.FsptArchRevision], 2=0D - jne ParamError=0D + jb ParamError=0D =0D ; UPD structure is compliant with FSP spec 2.4=0D mov rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]=0D @@ -273,7 +274,7 @@ CheckAddress: cmp byte [rsp + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2=0D jb ParamError=0D cmp byte [rsp + LoadMicrocodeParamsFsp24.FsptArchRevision], 2=0D - jne ParamError=0D + jb ParamError=0D =0D ; UPD structure is compliant with FSP spec 2.4=0D ; Is automatic size detection ?=0D @@ -337,8 +338,8 @@ ASM_PFX(EstablishStackFsp): ;=0D mov rax, ASM_PFX(PcdGet32 (PcdTemporaryRamBase))=0D mov esp, DWORD[rax]=0D - mov rax, ASM_PFX(PcdGet32 (PcdTemporaryRamSize))=0D - add esp, DWORD[rax]=0D + LOAD_TEMPORARY_RAM_SIZE rax=0D + add esp, eax=0D =0D sub esp, 4=0D mov dword[esp], DATA_LEN_OF_MCUD ; Size of the data region=0D @@ -349,7 +350,7 @@ ASM_PFX(EstablishStackFsp): cmp byte [rdx + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2= =0D jb ParamError1=0D cmp byte [rdx + LoadMicrocodeParamsFsp24.FsptArchRevision], 2=0D - je Fsp24UpdHeader=0D + jnb Fsp24UpdHeader=0D =0D ParamError1:=0D mov rax, 08000000000000002h=0D @@ -397,8 +398,8 @@ ContinueAfterUpdPush: ;=0D mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamBase))=0D mov edx, [ecx]=0D - mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize))=0D - add edx, [ecx]=0D + LOAD_TEMPORARY_RAM_SIZE rcx=0D + add edx, ecx=0D mov rcx, ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))=0D sub edx, [ecx]=0D mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamBase))=0D @@ -439,6 +440,12 @@ ASM_PFX(TempRamInitApi): ;=0D SAVE_BFV rbp=0D =0D + ;=0D + ; Read Fsp Info header and save in rsi=0D + ;=0D + CALL_RDI ASM_PFX(AsmGetFspInfoHeaderNoStack)=0D + xor rsi, rsi=0D + mov rsi, rax=0D ;=0D ; Save Input Parameter in YMM10=0D ;=0D @@ -448,10 +455,9 @@ ASM_PFX(TempRamInitApi): ;=0D ; Fall back to default UPD=0D ;=0D - CALL_RDI ASM_PFX(AsmGetFspInfoHeaderNoStack)=0D xor rcx, rcx=0D - mov ecx, DWORD [rax + 01Ch] ; Read FsptImageBaseAddress=0D - add ecx, DWORD [rax + 024h] ; Get Cfg Region base address = =3D FsptImageBaseAddress + CfgRegionOffset=0D + mov ecx, DWORD [rsi + 01Ch] ; Read FsptImageBaseAddress=0D + add ecx, DWORD [rsi + 024h] ; Get Cfg Region base address = =3D FsptImageBaseAddress + CfgRegionOffset=0D ParamValid:=0D SAVE_RCX=0D =0D @@ -463,6 +469,47 @@ ParamValid: or rax, rdx=0D SAVE_TS rax=0D =0D + mov rdx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize))=0D + mov edx, DWORD [rdx]=0D + ;=0D + ; Read ARCH2 UPD input value.=0D + ;=0D + mov ebx, DWORD [ecx + LoadMicrocodeParamsFsp24.FspTemporaryRamSize= ]=0D + ;=0D + ; As per spec, if Bootloader pass zero, use Fsp defined Size=0D + ; Irrespective of whether this UPD is supported or not, Fallback=0D + ; to Fsp defined size if input is zero.=0D + ;=0D + cmp ebx, 0=0D + jz UseTemporaryRamSizePcd=0D +=0D + xor rax, rax=0D + mov ax, WORD [rsi + 020h] ; Read ImageAttribute=0D + test ax, 16 ; check if Bit4 is set=0D + jnz ConsumeInputConfiguration=0D + ;=0D + ; Sometimes user may change input value even if it is not supported=0D + ; return error if input is Non-Zero and not same as PcdTemporaryRamSize.= =0D + ;=0D + cmp ebx, edx=0D + je UseTemporaryRamSizePcd=0D + mov rax, 08000000000000002h ; RETURN_INVALID_PARAMETER=0D + jmp TempRamInitExit=0D +ConsumeInputConfiguration:=0D + ;=0D + ; Read Fsp Arch2 revision=0D + cmp byte [ecx + LoadMicrocodeParamsFsp24.FsptArchRevision], 3=0D + jb UseTemporaryRamSizePcd=0D + ;=0D + ; Read ARCH2 UPD value and Save.=0D + ; Only low-32 bits of rbx/rdx holds the temporary ram size.=0D + ;=0D + SAVE_TEMPORARY_RAM_SIZE rbx=0D + jmp GotTemporaryRamSize=0D +UseTemporaryRamSizePcd:=0D + SAVE_TEMPORARY_RAM_SIZE rdx=0D +=0D +GotTemporaryRamSize:=0D ;=0D ; Sec Platform Init=0D ;=0D diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm b/IntelFsp2Pkg/FspS= ecCore/X64/FspHelper.nasm index 32a60270b8..61ebaa8ccf 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm @@ -28,7 +28,7 @@ ASM_PFX(FspInfoHeaderRelativeOff): global ASM_PFX(AsmGetFspInfoHeaderNoStack)=0D ASM_PFX(AsmGetFspInfoHeaderNoStack):=0D lea rax, [ASM_PFX(AsmGetFspInfoHeader)]=0D - lea rcx, [ASM_PFX(FspInfoHeaderRelativeOff)]=0D - mov ecx, [rcx]=0D - sub rax, rcx=0D + lea rsi, [ASM_PFX(FspInfoHeaderRelativeOff)]=0D + mov esi, [rsi]=0D + sub rax, rsi=0D jmp rdi=0D diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Include/Fs= pEas/FspApi.h index 40e063e944..27d5ec3a3c 100644 --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -139,7 +139,7 @@ typedef struct { ///=0D typedef struct {=0D ///=0D - /// Revision of the structure is 2 for this version of the specification= .=0D + /// Revision of the structure is 3 for this version of the specification= .=0D ///=0D UINT8 Revision;=0D UINT8 Reserved[3];=0D @@ -152,7 +152,8 @@ typedef struct { /// occurring during FSP execution.=0D ///=0D EFI_PHYSICAL_ADDRESS FspDebugHandler;=0D - UINT8 Reserved1[16];=0D + UINT32 FspTemporaryRamSize;=0D + UINT8 Reserved1[12];=0D } FSPT_ARCH2_UPD;=0D =0D ///=0D diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc b/IntelFsp2Pkg/= Include/SaveRestoreSseAvxNasm.inc index 002a5a1412..2168564e6d 100644 --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc @@ -201,6 +201,27 @@ movq rcx, xmm5=0D %endmacro=0D =0D +;=0D +; Save TemporaryRamSize to YMM10[192:255]=0D +; arg 1:general purpose register which holds TemporaryRamSize=0D +; Modified: XMM5 and YMM10[192:255]=0D +;=0D +%macro SAVE_TEMPORARY_RAM_SIZE 1=0D + LYMMN ymm10, xmm5, 1=0D + SXMMN xmm5, 1, %1=0D + SYMMN ymm10, 1, xmm5=0D + %endmacro=0D +=0D +;=0D +; Restore TemporaryRamSize from YMM10[192:255]=0D +; arg 1:general purpose register where to save TemporaryRamSize=0D +; Modified: XMM5 and %1=0D +;=0D +%macro LOAD_TEMPORARY_RAM_SIZE 1=0D + LYMMN ymm10, xmm5, 1=0D + LXMMN xmm5, %1, 1=0D + %endmacro=0D +=0D ;=0D ; YMM7[128:191] for calling stack=0D ; arg 1:Entry=0D diff --git a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/= SecRamInitData.c b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibS= ample/SecRamInitData.c index fb0d9a8683..316c2fa86a 100644 --- a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamI= nitData.c +++ b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamI= nitData.c @@ -49,8 +49,9 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA F= sptUpdDataPtr =3D { },=0D 0x00000020,=0D 0x00000000,=0D + 0x00000000,=0D {=0D - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D }=0D },=0D --=20 2.39.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#115527): https://edk2.groups.io/g/devel/message/115527 Mute This Topic: https://groups.io/mt/104376655/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-