From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: redhat.com, ip: 209.85.221.67, mailfrom: philmd@redhat.com) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by groups.io with SMTP; Wed, 29 May 2019 08:25:58 -0700 Received: by mail-wr1-f67.google.com with SMTP id t4so2094395wrx.7 for ; Wed, 29 May 2019 08:25:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:openpgp:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=soLfPjDaRmkcRbDmB+G1lqboXwrM6N6x7ZSaFlpIyp4=; b=sbqa7+gBJaUDG2T8JENcbOSHlFLeLDSi9B4p4vGOnAfDO1b2Yu3cmHuuYqCv83lC14 HV0WTklq+BkjNvj7PU57r0w/mbRz2pC/AB3daJU/QQshP5GvzZyUMalLy71lT1j9oWcc aJXb3tCX6u/d1aEGU0o/wEtw6bR+A+ROHFsb1KEVk1EsGMTUF0ezTPpoc7PNuKJ4B697 TeeZVaSP5kLM3YBSipUpHyI4SpDysJuCqB61wtBfUUmMZWwEJppAN0ZiDNUKJCz9x205 ix9PPbMvYFvB7YGiI3xr3TCwXuTixhccSxeMTkYyOqOnF2kxg/02EuYI+HPKjy6fZGHQ ZfAA== X-Gm-Message-State: APjAAAV0iAI3i+GwVYQ6yRiVgenUYUMR6ANmkixsdspnGCq11uLs6i4l XV7XpNkY8WbjxqMPk3f8HrF8TQ== X-Google-Smtp-Source: APXvYqw06sjN5nTnzywHkwcYoYyXodAbQ/fZr76MlT91hzQQ/Os3Orrkw3DuespvInDgLFWO6LFyjw== X-Received: by 2002:adf:9e4c:: with SMTP id v12mr4546945wre.312.1559143552027; Wed, 29 May 2019 08:25:52 -0700 (PDT) Return-Path: Received: from [10.201.33.53] ([195.166.127.210]) by smtp.gmail.com with ESMTPSA id u19sm15275303wmu.41.2019.05.29.08.25.50 (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Wed, 29 May 2019 08:25:51 -0700 (PDT) Subject: Re: [edk2-devel] [PATCH for-edk2-stable201905 4/6] Revert "OvmfPkg/PlatformPei: assign PciSize on both i440fx/q35 branches explicitly" To: devel@edk2.groups.io, lersek@redhat.com Cc: Ard Biesheuvel , Gerd Hoffmann , Jordan Justen References: <20190529151209.17503-1-lersek@redhat.com> <20190529151209.17503-5-lersek@redhat.com> From: =?UTF-8?B?UGhpbGlwcGUgTWF0aGlldS1EYXVkw6k=?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: <5ebff730-cee0-dda9-fda8-f8b0ca5de05e@redhat.com> Date: Wed, 29 May 2019 17:25:50 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190529151209.17503-5-lersek@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 5/29/19 5:12 PM, Laszlo Ersek wrote: > This reverts commit 60e95bf5094fbb9b728729ccfaf32184b3662317. > > The original fix for > triggered a bug / incorrect assumption in QEMU. > > QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above > it. When the firmware doesn't satisfy this assumption, QEMU generates an > \_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the > firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign > 32-bit MMIO BARs. > > Working around the problem in the firmware looks less problematic than > fixing QEMU. Revert the original changes first, before implementing an > alternative fix. > > Cc: Ard Biesheuvel > Cc: Gerd Hoffmann > Cc: Jordan Justen > Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859 > Signed-off-by: Laszlo Ersek Reviewed-by: Philippe Mathieu-Daude > --- > OvmfPkg/PlatformPei/Platform.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c > index 5e0a15484230..0876316eefbc 100644 > --- a/OvmfPkg/PlatformPei/Platform.c > +++ b/OvmfPkg/PlatformPei/Platform.c > @@ -190,10 +190,8 @@ MemMapInitialization ( > ASSERT (TopOfLowRam <= PciExBarBase); > ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB); > PciBase = (UINT32)(PciExBarBase + SIZE_256MB); > - PciSize = 0xFC000000 - PciBase; > } else { > PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; > - PciSize = 0xFC000000 - PciBase; > } > > // > @@ -209,6 +207,7 @@ MemMapInitialization ( > // 0xFED20000 gap 896 KB > // 0xFEE00000 LAPIC 1 MB > // > + PciSize = 0xFC000000 - PciBase; > AddIoMemoryBaseSizeHob (PciBase, PciSize); > PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase); > ASSERT_RETURN_ERROR (PcdStatus); >