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cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1304.22; Mon, 31 Jul 2017 20:27:19 +0000 Cc: brijesh.singh@amd.com, "edk2-devel@lists.01.org" , Tom Lendacky , Laszlo Ersek , Jordan Justen To: Ard Biesheuvel References: <1501529474-20550-1-git-send-email-brijesh.singh@amd.com> <1501529474-20550-3-git-send-email-brijesh.singh@amd.com> From: Brijesh Singh Message-ID: <5f2b17f8-9872-c1ff-715d-96e3158e6df1@amd.com> Date: Mon, 31 Jul 2017 15:27:16 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: DM3PR12CA0065.namprd12.prod.outlook.com (10.161.151.33) To CY1PR12MB0150.namprd12.prod.outlook.com (10.161.173.20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 424ed955-f405-4b4a-15c0-08d4d8528b29 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; 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20:Bvip1epo5Hmzl/6iCx1HkKS68xMTRVYtErJZu17UEzK40nk6WLz0CMJprSi9sf1dNM+hJJoUQzVx9MigYZHXP0Yr8/4rhgFJlcKDUu8SIX7XPwMMSvOsOyX9h5fvZp/PuGR1mjsiTHLKk3+geIrtjQTYSLbXlhjlRT+J17zKppt8Nl0DzaN9evyiJV7kO93Ar48wpAbG+WY5Qd9dZ9TKBr50gvlU5wA89/HAJ0/pZpZuaCaJN15tFe3+madSsY40 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Jul 2017 20:27:19.5819 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB0150 Subject: Re: [PATCH v1 2/4] OvmfPkg: IommuDxe: Provide support for mapping BusMasterCommonBuffer operation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 31 Jul 2017 20:25:14 -0000 Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit On 07/31/2017 02:49 PM, Ard Biesheuvel wrote: > On 31 July 2017 at 20:31, Brijesh Singh wrote: >> The current implementation was making assumption that AllocateBuffer() >> returns a buffer with C-bit cleared. Hence when we were asked to >> Map() with BusMasterCommonBuffer, we do not change the C-bit on >> host buffer. >> >> In previous patch, we changed the AllocateBuffer() to not clear >> C-bit during allocation. The patch adds support for handling the >> BusMasterCommonBuffer operations when SEV is active. >> >> A typical DMA Bus master Common Operation follows the below step: >> >> 1. Client calls AllocateBuffer() to allocate a common buffer >> 2. Client fill some data in common buffer (optional) >> 3. Client calls Map() with BusMasterCommonBuffer >> 4. Programs the DMA bus master with the device address returned by Map() >> 5. The common buffer can now be accessed equally by the processor and >> the DMA bus master. >> 6. Client calls Unmap() >> 7. Client calls FreeBuffer() >> >> In order to handle steps #2 (in which common buffer may contain >> data), we perform in-place encryption to ensure that device >> address returned by the Map() contains the correct data after >> we clear the C-bit during Map(). >> >> In my measurement I do not see any noticable perform degradation when >> performing in-place encryption/decryption on common buffer. >> >> Suggested-by: Laszlo Ersek >> Contributed-under: TianoCore Contribution Agreement 1.0 >> Cc: Laszlo Ersek >> Cc: Jordan Justen >> Signed-off-by: Brijesh Singh >> --- >> OvmfPkg/IoMmuDxe/AmdSevIoMmu.c | 190 +++++++++++++++++--- >> 1 file changed, 164 insertions(+), 26 deletions(-) >> > > Hello Brijesh, > > I haven't looked in detail at the existing code, but please don't > conflate the device address with the address of a bounce buffer. These > are very different things, although the confusion is understandable > (and precedented) when not used to dealing with non-1:1 DMA. > > The device address is what gets programmed into the device's DMA > registers. If there is a fixed [non-zero] offset between the device's > view of memory and the host's (as may be the case with PCI, or > generally when using an IOMMU), then the device is the only one who > should attempt to perform memory accesses using this address. So > please void SetMem() or other CPU dereferences involving the device > address, and treat it as an opaque handle instead. > > In your case, you are dealing with a bounce buffer. So call it bounce > buffer in the MapInfo struct. Imagine when dealing with a non-linear > host to PCI mapping, you will still need to perform an additional > translation to derive the device address from the bounce buffer > address. > Agreed. Initially, AmdSevIoMmu.c code was derived from PciRootBridgeIo and MAP_INFO structure was literally copied. I will probably send a separate patch to fix the structure member and update the comments to reflect its true meaning. Thanks Brijesh