From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::641; helo=mail-pl1-x641.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl1-x641.google.com (mail-pl1-x641.google.com [IPv6:2607:f8b0:4864:20::641]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 01B5A21962301 for ; Tue, 12 Feb 2019 07:22:37 -0800 (PST) Received: by mail-pl1-x641.google.com with SMTP id s1so1448968plp.9 for ; Tue, 12 Feb 2019 07:22:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=qRPstJZTXks5D6Fsi4tIMN9BivFPZ/SU3W00ativmMk=; b=w4hgCMCY5nxpV1t0VxVpxjCpkgzdceVZrBCfse7JKgrx9FJbIGL1+BjFCSJG1sRAIW 83dy63Ye+Xc4Xu3guen2EH8KT3xvlV/2dSDU4baMdu+LJ1ajWoOZbPaWfJJ2aE/R5LyS igNHF99eLBpsMoRlknbAgShcJYnetIYdhnQWcbqS2BnZoSQchURFmckzluzuCEmWDYL+ gh/vV01XPZPQgahi7cc3p0F5bRe6+M3AehUP7Gt54VvrI6+54oboW7zqBSLUes2Zi0O1 Nw1l6QHMXpWHhGENajZtP+ILzmMP/8dh5qygf1NdjBc6pwZKUPtqipeVAOA+HUB/8vDG 5nEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=qRPstJZTXks5D6Fsi4tIMN9BivFPZ/SU3W00ativmMk=; b=VG1PFRJzX3BwRxTdobERpNWZ97BXDE1YvgrkzX+2nILn8iQyt6Hb/rK6VKyw1jZO2M p7KfaAyI1nmagx6ulpi6ZGobAD3nU4Ndo+zkhY/IdaqVllet2aWnXg+IvpOAoHpelWap 013dirax0C8nXgupjDEmEDYIQ/McE+dmAqN5ywh3hJp5jwCfjGlAdoJOtpCOAyYGzusb 30fH3rnNniJSI0uDMxWettl5su6X1v4Tj6vZhhIko6b8qrtVywyh5O8KF/JC8SZS0NgV rrA4U2eF3xRbXtTSogShF1nBPYXkg4BJNT1G3+6YyJF1xm9Aqp4DuBqasIkcuWtxCNiB hqNg== X-Gm-Message-State: AHQUAuZrLXIwhboyBOcjtt+CtG2DVlSWuXz8xrxIoPSc41eq6p8n5E/o sVcaAoM9zNJ/MJlMGJqFtsbl+A== X-Google-Smtp-Source: AHgI3IaMcZFTuFJ4HNgmD4UYaOqCkejBnHgus7NPvavuxDkqsPJzLImVqUlmbMDq0SB4eKqNqENGrg== X-Received: by 2002:a17:902:2a47:: with SMTP id i65mr4543791plb.237.1549984957476; Tue, 12 Feb 2019 07:22:37 -0800 (PST) Received: from [10.15.0.66] ([64.64.108.250]) by smtp.gmail.com with ESMTPSA id 125sm20048710pfx.159.2019.02.12.07.22.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Feb 2019 07:22:36 -0800 (PST) To: Leif Lindholm Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, zhangfeng56@huawei.com References: <20190201133436.10500-1-ming.huang@linaro.org> <20190201133436.10500-12-ming.huang@linaro.org> <20190211194646.624grnmi34inexvd@bivouac.eciton.net> From: Ming Huang Message-ID: <5fba3b99-5318-ec7b-54ef-086cd13f7c40@linaro.org> Date: Tue, 12 Feb 2019 23:22:24 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.0 MIME-Version: 1.0 In-Reply-To: <20190211194646.624grnmi34inexvd@bivouac.eciton.net> Subject: Re: [PATCH edk2-platforms v1 11/16] Hisilicon/D06: Add Setup Item "Support DPC" X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Feb 2019 15:22:38 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 2/12/2019 3:46 AM, Leif Lindholm wrote: > On Fri, Feb 01, 2019 at 09:34:31PM +0800, Ming Huang wrote: >> Add setup item "Support DPC" to enable or disable PCIe DPC >> (Downstream Port Containment). > > This patch also seems to disable the SRIOV configuration and delete a > lot of ports. Can you explain how this is related? The pcie menu is suppressed for original code as these menus are not ready, this patch remove the suppression for pcie menu, so delete these menus for now. Thanks. > > / > Leif > >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ming Huang >> --- >> Silicon/Hisilicon/Include/Library/OemConfigData.h | 1 + >> Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr | 2 - >> Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c | 4 + >> Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr | 197 +------------------- >> Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni | 3 +- >> 5 files changed, 10 insertions(+), 197 deletions(-) >> >> diff --git a/Silicon/Hisilicon/Include/Library/OemConfigData.h b/Silicon/Hisilicon/Include/Library/OemConfigData.h >> index f120e3123c83..c0097d0829f0 100644 >> --- a/Silicon/Hisilicon/Include/Library/OemConfigData.h >> +++ b/Silicon/Hisilicon/Include/Library/OemConfigData.h >> @@ -49,6 +49,7 @@ typedef struct { >> UINT8 OSWdtAction; >> /*PCIe Config*/ >> UINT8 PcieSRIOVSupport; >> + UINT8 PcieDPCSupport; >> UINT8 PciePort[PCIE_MAX_TOTAL_PORTS]; >> UINT8 PcieLinkSpeedPort[PCIE_MAX_TOTAL_PORTS]; >> UINT8 PcieLinkDeEmphasisPort[PCIE_MAX_TOTAL_PORTS]; >> diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr >> index 08236704fbfe..93ccb99bdc67 100644 >> --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr >> +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.vfr >> @@ -62,11 +62,9 @@ formset >> prompt = STRING_TOKEN(STR_IBMC_CONFIG_FORM_TITLE), >> help = STRING_TOKEN(STR_IBMC_CONFIG_FORM_HELP); >> >> - suppressif TRUE; >> goto PCIE_CONFIG_FORM_ID, >> prompt = STRING_TOKEN(STR_PCIE_CONFIG_FORM_TITLE), >> help = STRING_TOKEN(STR_PCIE_CONFIG_FORM_HELP); >> - endif; >> >> goto MISC_CONFIG_FORM_ID, >> prompt = STRING_TOKEN(STR_MISC_CONFIG_FORM_TITLE), >> diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c >> index 6668103af027..be4ce8820f73 100644 >> --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c >> +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c >> @@ -290,6 +290,10 @@ OemConfigUiLibConstructor ( >> Configuration.OSWdtTimeout = 5; >> Configuration.OSWdtAction = 1; >> // >> + //Set the default value of the PCIe option >> + // >> + Configuration.PcieDPCSupport = 0; >> + // >> //Set the default value of the Misc option >> // >> Configuration.EnableSmmu = 1; >> diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr >> index 7cf7cdd29ba2..c65907fe846e 100644 >> --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr >> +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr >> @@ -17,203 +17,12 @@ >> form formid = PCIE_CONFIG_FORM_ID, >> title = STRING_TOKEN (STR_PCIE_CONFIG_FORM_TITLE); >> >> - goto VFR_FORMID_PCIE_SOCKET0, >> - prompt = STRING_TOKEN (STR_PCIE_CPU_0_PROMPT), >> - help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP); >> - >> - goto VFR_FORMID_PCIE_SOCKET1, >> - prompt = STRING_TOKEN (STR_PCIE_CPU_1_PROMPT), >> - help = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP); >> - >> - oneof varid = OEM_CONFIG_DATA.PcieSRIOVSupport, >> - prompt = STRING_TOKEN (STR_SRIOV_SUPPORT_PROMPT), >> - help = STRING_TOKEN (STR_SRIOV_SUPPORT_HELP), >> + oneof varid = OEM_CONFIG_DATA.PcieDPCSupport, >> + prompt = STRING_TOKEN (STR_DPC_SUPPORT_PROMPT), >> + help = STRING_TOKEN (STR_DPC_SUPPORT_HELP), >> option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED; >> option text = STRING_TOKEN (STR_ENABLE), value = 1, flags = RESET_REQUIRED; >> endoneof; >> >> endform; >> >> -form formid = VFR_FORMID_PCIE_SOCKET0, >> - title = STRING_TOKEN(STR_PCIE_CPU_0_PROMPT); >> - >> - goto VFR_FORMID_PCIE_PORT2, >> - prompt = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT), >> - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); >> - >> - goto VFR_FORMID_PCIE_PORT4, >> - prompt = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT), >> - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); >> - >> - goto VFR_FORMID_PCIE_PORT5, >> - prompt = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT), >> - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); >> - >> - goto VFR_FORMID_PCIE_PORT6, >> - prompt = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT), >> - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); >> - >> - goto VFR_FORMID_PCIE_PORT7, >> - prompt = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT), >> - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_SOCKET1, >> - title = STRING_TOKEN(STR_PCIE_CPU_1_PROMPT); >> - goto VFR_FORMID_PCIE_PORT10, >> - prompt = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT), >> - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); >> - >> - goto VFR_FORMID_PCIE_PORT12, >> - prompt = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT), >> - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); >> - >> - goto VFR_FORMID_PCIE_PORT13, >> - prompt = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT), >> - help = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP); >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT0, >> - title = STRING_TOKEN(STR_PCIE_PORT_0_PROMPT); >> - #undef INDEX >> - #define INDEX 0 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT1, >> - title = STRING_TOKEN(STR_PCIE_PORT_1_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 1 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT2, >> - title = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 2 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT3, >> - title = STRING_TOKEN(STR_PCIE_PORT_3_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 3 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT4, >> - title = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 4 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT5, >> - title = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 5 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT6, >> - title = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 6 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT7, >> - title = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 7 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT8, >> - title = STRING_TOKEN(STR_PCIE_PORT_8_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 8 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT9, >> - title = STRING_TOKEN(STR_PCIE_PORT_9_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 9 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT10, >> - title = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 10 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT11, >> - title = STRING_TOKEN(STR_PCIE_PORT_11_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 11 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT12, >> - title = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 12 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT13, >> - title = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 13 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT14, >> - title = STRING_TOKEN(STR_PCIE_PORT_14_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 14 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> -form formid = VFR_FORMID_PCIE_PORT15, >> - title = STRING_TOKEN(STR_PCIE_PORT_15_PROMPT); >> - >> - #undef INDEX >> - #define INDEX 15 >> - #include "PciePortConfig.hfr" >> - >> -endform; >> - >> diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni >> index d87d30f975b8..0127ea952dee 100644 >> --- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni >> +++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni >> @@ -26,7 +26,8 @@ >> #string STR_PCIE_CPU_1_PROMPT #language en-US "CPU 1 PCIE Configuration" >> #string STR_SRIOV_SUPPORT_PROMPT #language en-US "SRIOV" >> #string STR_SRIOV_SUPPORT_HELP #language en-US "This option enables / disables the SRIOV function" >> - >> +#string STR_DPC_SUPPORT_PROMPT #language en-US "Support DPC" >> +#string STR_DPC_SUPPORT_HELP #language en-US "This option enables / disables the DPC function" >> #string STR_PCIE_PORT_PROMPT_HELP #language en-US "Press to config this port." >> #string STR_PCIE_PORT_0_NULL_PROMPT #language en-US "" >> #string STR_PCIE_PORT_0_PROMPT #language en-US "CPU 0 Pcie - Port 0" >> -- >> 2.9.5 >>