From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id E204B941468 for ; Wed, 28 Feb 2024 08:30:05 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=06CjySy/1p4yLAarbSMvuFLainFsWyl8DsFK6/O8HmM=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1709109004; v=1; b=te+PMDSYjaQJfnCCuYkeaxKUXqJ7Kv4huYZGrJv05H0Vsc1xlZxgbukJ59uTFMxuQn2jgc6J 9vVioA4VxIW/G++D3ucwl//I+QIPoXRRmRF5LYBphn7X2eopr7+lQRLvi7g4uPntdZH+FB27eNQ UVnick3kt0aS23WyYuYKNE1A= X-Received: by 127.0.0.2 with SMTP id DIQKYY7687511xUqYmpx7Bfv; Wed, 28 Feb 2024 00:30:04 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by mx.groups.io with SMTP id smtpd.web10.9056.1709109004030954928 for ; Wed, 28 Feb 2024 00:30:04 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10996"; a="3418111" X-IronPort-AV: E=Sophos;i="6.06,190,1705392000"; d="scan'208";a="3418111" X-Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2024 00:30:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,190,1705392000"; d="scan'208";a="7293348" X-Received: from vamsikr1-mobl.gar.corp.intel.com (HELO cbduggap-mobl.gar.corp.intel.com) ([10.215.177.179]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2024 00:30:01 -0800 From: "cbduggap" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone , Chiu Chasel , Duggapu Chinni B Subject: [edk2-devel] [PATCH v4] IntelFsp2Pkg: Fsp 2.x Changes Date: Wed, 28 Feb 2024 13:59:36 +0530 Message-Id: <602812ed6f70bd983c30924dc6a3619e7a3bb1b5.1709108958.git.chinni.b.duggapu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chinni.b.duggapu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: mIDNeomWHSY4xMRxEJkakgL8x7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=te+PMDSY; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Changes to support spec changes 1. Remove usage of Pcd. 2. Change code to validate the Temporary Ram size input. 3. Consume the input saved in YMM Register Cc: Sai Chaganty Cc: Nate DeSimone Cc: Chiu Chasel Cc: Duggapu Chinni B Signed-off-by: Duggapu Chinni B --- IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf | 2 +- IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 2 +- IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf | 1 + .../FspSecCore/Ia32/Fsp24ApiEntryM.nasm | 1 - .../FspSecCore/Ia32/FspApiEntryM.nasm | 1 - .../FspSecCore/Ia32/FspApiEntryT.nasm | 70 ++++++++++++++--- .../FspSecCore/Ia32/SaveRestoreSseNasm.inc | 11 +++ IntelFsp2Pkg/FspSecCore/SecFsp.c | 17 +++- IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 4 +- IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 78 +++++++++++++++---- IntelFsp2Pkg/Include/FspEas/FspApi.h | 5 +- .../Include/SaveRestoreSseAvxNasm.inc | 21 +++++ IntelFsp2Pkg/IntelFsp2Pkg.dec | 5 ++ .../SecRamInitData.c | 3 +- 14 files changed, 185 insertions(+), 36 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf b/IntelFsp2Pkg/FspSe= cCore/Fsp24SecCoreM.inf index cb011f99f9..cf8cb2eda9 100644 --- a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf +++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf @@ -63,11 +63,11 @@ =0D [Pcd]=0D gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES= =0D - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES= =0D gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES= =0D gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES= =0D gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported ## CONSUMES= =0D gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize ## CONSUMES= =0D + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUMES= =0D =0D [Ppis]=0D gEfiTemporaryRamSupportPpiGuid ## PRODUCES= =0D diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf b/IntelFsp2Pkg/FspSecC= ore/FspSecCoreM.inf index 8029832235..717941c33f 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf @@ -62,11 +62,11 @@ =0D [Pcd]=0D gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES= =0D - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES= =0D gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES= =0D gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES= =0D gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported ## CONSUMES= =0D gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize ## CONSUMES= =0D + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUMES= =0D =0D [Ppis]=0D gEfiTemporaryRamSupportPpiGuid ## PRODUCES= =0D diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf b/IntelFsp2Pkg/FspSecC= ore/FspSecCoreT.inf index e5a6eaa164..05c0d5f48b 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf @@ -51,6 +51,7 @@ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES= =0D gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES= =0D gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES= =0D + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUMES= =0D =0D [Ppis]=0D gEfiTemporaryRamSupportPpiGuid ## PRODUCES= =0D diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm b/IntelFsp2Pk= g/FspSecCore/Ia32/Fsp24ApiEntryM.nasm index 15f8ecea83..5fa5c03569 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm @@ -11,7 +11,6 @@ ; Following are fixed PCDs=0D ;=0D extern ASM_PFX(PcdGet32(PcdTemporaryRamBase))=0D -extern ASM_PFX(PcdGet32(PcdTemporaryRamSize))=0D extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))=0D extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))=0D =0D diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryM.nasm index 61ab4612a3..861cce4d01 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm @@ -11,7 +11,6 @@ ; Following are fixed PCDs=0D ;=0D extern ASM_PFX(PcdGet32(PcdTemporaryRamBase))=0D -extern ASM_PFX(PcdGet32(PcdTemporaryRamSize))=0D extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))=0D extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))=0D =0D diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryT.nasm index 900126b93b..020599ba89 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -16,6 +16,7 @@ extern ASM_PFX(PcdGet32 (PcdTemporaryRamBase))=0D extern ASM_PFX(PcdGet32 (PcdTemporaryRamSize))=0D extern ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))=0D +extern ASM_PFX(PcdGet32 (PcdGlobalDataPointerAddress))=0D =0D ;=0D ; Following functions will be provided in PlatformSecLib=0D @@ -109,7 +110,8 @@ struc LoadMicrocodeParamsFsp24 .FsptArchReserved: resb 3=0D .FsptArchLength: resd 1=0D .FspDebugHandler resq 1=0D - .FsptArchUpd: resd 4=0D + .FspTemporaryRamSize: resd 1 ; Supported only if ArchRevison i= s >=3D 3=0D + .FsptArchUpd: resd 3=0D ; }=0D ; FSPT_CORE_UPD {=0D .MicrocodeCodeAddr: resq 1=0D @@ -267,7 +269,7 @@ ASM_PFX(LoadMicrocodeDefault): cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2=0D jb Fsp20UpdHeader=0D cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2=0D - je Fsp24UpdHeader=0D + jae Fsp24UpdHeader=0D jmp Fsp22UpdHeader=0D =0D Fsp20UpdHeader:=0D @@ -405,7 +407,7 @@ CheckAddress: cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2=0D jb Fsp20UpdHeader1=0D cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2=0D - je Fsp24UpdHeader1;=0D + jae Fsp24UpdHeader1;=0D jmp Fsp22UpdHeader1=0D =0D Fsp20UpdHeader1:=0D @@ -497,7 +499,15 @@ ASM_PFX(EstablishStackFsp): ; Enable FSP STACK=0D ;=0D mov esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]=0D - add esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]=0D + LOAD_TEMPORARY_RAM_SIZE ecx=0D + add esp, ecx=0D + ;=0D + ; Save TemporaryRam size in PcdGlobalDataPointerAddress=0D + ; which will be used in FSP-M if required.=0D + ;=0D + mov rax, ASM_PFX(PcdGet32 (PcdGlobalDataPointerAddress))=0D + mov eax, DWORD[rax]=0D + mov DWORD[eax], ecx=0D =0D push DATA_LEN_OF_MCUD ; Size of the data region=0D push 4455434Dh ; Signature of the data region 'MCUD'=0D @@ -506,7 +516,7 @@ ASM_PFX(EstablishStackFsp): cmp byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2= =0D jb Fsp20UpdHeader2=0D cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2=0D - je Fsp24UpdHeader2=0D + jae Fsp24UpdHeader2=0D jmp Fsp22UpdHeader2=0D =0D Fsp20UpdHeader2:=0D @@ -554,12 +564,13 @@ ContinueAfterUpdPush: ;=0D ; Set ECX/EDX to the BootLoader temporary memory range=0D ;=0D - mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]=0D - mov edx, ecx=0D - add edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]=0D + mov edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]=0D + LOAD_TEMPORARY_RAM_SIZE ecx=0D + add edx, ecx=0D sub edx, [ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))]=0D + mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]=0D =0D - cmp ecx, edx ;If PcdFspReservedBufferSize >=3D PcdTemporary= RamSize, then error.=0D + cmp ecx, edx ;If PcdFspReservedBufferSize >=3D TemporaryRam= Size, then error.=0D jb EstablishStackFspSuccess=0D mov eax, 80000003h ;EFI_UNSUPPORTED=0D jmp EstablishStackFspExit=0D @@ -599,6 +610,47 @@ ASM_PFX(TempRamInitApi): CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param=0D SAVE_ECX ; save UPD param to slot 3 in xmm= 6=0D =0D + mov edx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize))=0D + mov edx, DWORD [edx]=0D + ;=0D + ; Read ARCH2 UPD input value.=0D + ;=0D + mov ebx, DWORD [ecx + LoadMicrocodeParamsFsp24.FspTemporaryRamSize= ]=0D + ;=0D + ; As per spec, if Bootloader pass zero, use Fsp defined Size=0D + ; Irrespective of whether this UPD is supported or not, Fallback=0D + ; to Fsp defined size if input is zero.=0D + ;=0D + cmp ebx, 0=0D + jz UseTemporaryRamSizePcd=0D +=0D + xor eax, eax=0D + mov ax, WORD [esi + 020h] ; Read ImageAttribute=0D + test ax, 16 ; check if Bit4 is set=0D + jnz ConsumeInputConfiguration=0D + ;=0D + ; Sometimes user may change input value even if it is not supported=0D + ; return error if input is Non-Zero and not same as PcdTemporaryRamSize.= =0D + ;=0D + cmp ebx, edx=0D + je UseTemporaryRamSizePcd=0D + mov eax, 080000002h ; RETURN_INVALID_PARAMETER=0D + jmp TempRamInitExit=0D +ConsumeInputConfiguration:=0D + ;=0D + ; Read Fsp Arch2 revision=0D + ;=0D + cmp byte [ecx + LoadMicrocodeParamsFsp24.FsptArchRevision], 3=0D + jb UseTemporaryRamSizePcd=0D + ;=0D + ; Read ARCH2 UPD value and Save.=0D + ;=0D + SAVE_TEMPORARY_RAM_SIZE ebx=0D + jmp GotTemporaryRamSize=0D +UseTemporaryRamSizePcd:=0D + SAVE_TEMPORARY_RAM_SIZE edx=0D +GotTemporaryRamSize:=0D + LOAD_ECX=0D ;=0D ; Sec Platform Init=0D ;=0D diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFsp= 2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc index 016f943b43..4d6ec1e984 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc @@ -128,6 +128,17 @@ SXMMN xmm5, 1, eax=0D %endmacro=0D =0D +;=0D +; XMM5 slot 2 for TemporaryRamSize=0D +;=0D +%macro LOAD_TEMPORARY_RAM_SIZE 1=0D + LXMMN xmm5, %1, 2=0D + %endmacro=0D +=0D +%macro SAVE_TEMPORARY_RAM_SIZE 1=0D + SXMMN xmm5, 2, %1=0D + %endmacro=0D +=0D %macro ENABLE_SSE 0=0D ;=0D ; Initialize floating point units=0D diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/Sec= Fsp.c index 11be1f97ca..8b41968760 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c @@ -47,7 +47,8 @@ FspGetExceptionHandler ( VOID=0D EFIAPI=0D SecGetPlatformData (=0D - IN OUT FSP_GLOBAL_DATA *FspData=0D + IN OUT FSP_GLOBAL_DATA *FspData,=0D + IN UINT32 TemporaryRamSize=0D )=0D {=0D FSP_PLAT_DATA *FspPlatformData;=0D @@ -68,10 +69,13 @@ SecGetPlatformData ( FspPlatformData->CodeRegionBase =3D 0;=0D FspPlatformData->CodeRegionSize =3D 0;=0D =0D + if (TemporaryRamSize =3D=3D 0 || TemporaryRamSize =3D=3D 0xFFFFFFFF) {=0D + return;=0D + }=0D //=0D // Pointer to the size field=0D //=0D - TopOfCar =3D PcdGet32 (PcdTemporaryRamBase) + PcdGet32 (PcdTemporaryRamS= ize);=0D + TopOfCar =3D PcdGet32 (PcdTemporaryRamBase) + TemporaryRamSize;=0D StackPtr =3D (UINT32 *)(TopOfCar - sizeof (UINT32));=0D =0D if (*(StackPtr - 1) =3D=3D FSP_MCUD_SIGNATURE) {=0D @@ -123,7 +127,14 @@ FspGlobalDataInit ( VOID *FspmUpdDataPtr;=0D CHAR8 ImageId[9];=0D UINTN Idx;=0D + UINTN *TopOfCar;=0D =0D + //=0D + // If TempRam is initilized using FspTempRamInitApi (), GlobalDataPointe= r=0D + // will point to the Top of the Car and any Data that FspTempRamInitApi= =0D + // wants to Handoff to later stages will be pushed on to the Top of the = car.=0D + //=0D + TopOfCar =3D *(VOID **)(UINTN)PcdGet32 (PcdGlobalDataPointerAddress);=0D //=0D // Set FSP Global Data pointer=0D //=0D @@ -147,7 +158,7 @@ FspGlobalDataInit ( // It may have multiple FVs, so look into the last one for FSP header=0D //=0D PeiFspData->FspInfoHeader =3D (FSP_INFO_HEADER *)(UINTN)AsmGetFspInfoHea= der ();=0D - SecGetPlatformData (PeiFspData);=0D + SecGetPlatformData (PeiFspData, (UINTN)TopOfCar);=0D =0D //=0D // Set API calling mode=0D diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c b/IntelFsp2Pkg/FspSecCo= re/SecFspApiChk.c index 5f59938518..33aaac66c1 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c @@ -42,9 +42,7 @@ FspApiCallingCheck ( //=0D // FspMemoryInit check=0D //=0D - if (((UINTN)FspData !=3D MAX_ADDRESS) && ((UINTN)FspData !=3D MAX_UINT= 32)) {=0D - Status =3D EFI_UNSUPPORTED;=0D - } else if (ApiParam =3D=3D NULL) {=0D + if (ApiParam =3D=3D NULL) {=0D Status =3D EFI_SUCCESS;=0D } else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) {=0D Status =3D EFI_INVALID_PARAMETER;=0D diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/F= spSecCore/X64/FspApiEntryT.nasm index 698bb063a7..4a1da9f718 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -16,6 +16,7 @@ extern ASM_PFX(PcdGet32 (PcdTemporaryRamBase))=0D extern ASM_PFX(PcdGet32 (PcdTemporaryRamSize))=0D extern ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))=0D +extern ASM_PFX(PcdGet32 (PcdGlobalDataPointerAddress))=0D =0D ;=0D ; Following functions will be provided in PlatformSecLib=0D @@ -76,7 +77,8 @@ struc LoadMicrocodeParamsFsp24 .FsptArchReserved: resb 3=0D .FsptArchLength: resd 1=0D .FspDebugHandler resq 1=0D - .FsptArchUpd: resd 4=0D + .FspTemporaryRamSize: resd 1 ; Supported only if ArchRevison is= >=3D 3=0D + .FsptArchUpd: resd 3=0D ; }=0D ; FSPT_CORE_UPD {=0D .MicrocodeCodeAddr: resq 1=0D @@ -163,7 +165,7 @@ ASM_PFX(LoadMicrocodeDefault): cmp byte [rsp + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2=0D jb ParamError=0D cmp byte [rsp + LoadMicrocodeParamsFsp24.FsptArchRevision], 2=0D - jne ParamError=0D + jb ParamError=0D =0D ; UPD structure is compliant with FSP spec 2.4=0D mov rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]=0D @@ -273,7 +275,7 @@ CheckAddress: cmp byte [rsp + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2=0D jb ParamError=0D cmp byte [rsp + LoadMicrocodeParamsFsp24.FsptArchRevision], 2=0D - jne ParamError=0D + jb ParamError=0D =0D ; UPD structure is compliant with FSP spec 2.4=0D ; Is automatic size detection ?=0D @@ -337,9 +339,16 @@ ASM_PFX(EstablishStackFsp): ;=0D mov rax, ASM_PFX(PcdGet32 (PcdTemporaryRamBase))=0D mov esp, DWORD[rax]=0D - mov rax, ASM_PFX(PcdGet32 (PcdTemporaryRamSize))=0D - add esp, DWORD[rax]=0D -=0D + LOAD_TEMPORARY_RAM_SIZE rax=0D + add esp, eax=0D + ;=0D + ; Save top of the TemporaryRam in PcdGlobalDataPointerAddress=0D + ; where the FspTempRamInitAPI information is pushed as part of below cod= e=0D + ; which will be used in other Fsp APIs to retrive the same.=0D + ;=0D + mov rax, ASM_PFX(PcdGet32 (PcdGlobalDataPointerAddress))=0D + mov eax, DWORD[rax]=0D + mov DWORD[eax], esp=0D sub esp, 4=0D mov dword[esp], DATA_LEN_OF_MCUD ; Size of the data region=0D sub esp, 4=0D @@ -349,7 +358,7 @@ ASM_PFX(EstablishStackFsp): cmp byte [rdx + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2= =0D jb ParamError1=0D cmp byte [rdx + LoadMicrocodeParamsFsp24.FsptArchRevision], 2=0D - je Fsp24UpdHeader=0D + jnb Fsp24UpdHeader=0D =0D ParamError1:=0D mov rax, 08000000000000002h=0D @@ -397,8 +406,8 @@ ContinueAfterUpdPush: ;=0D mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamBase))=0D mov edx, [ecx]=0D - mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize))=0D - add edx, [ecx]=0D + LOAD_TEMPORARY_RAM_SIZE rcx=0D + add edx, ecx=0D mov rcx, ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))=0D sub edx, [ecx]=0D mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamBase))=0D @@ -439,6 +448,14 @@ ASM_PFX(TempRamInitApi): ;=0D SAVE_BFV rbp=0D =0D + ;=0D + ; Save timestamp into YMM6=0D + ;=0D + rdtsc=0D + shl rdx, 32=0D + or rax, rdx=0D + SAVE_TS rax=0D +=0D ;=0D ; Save Input Parameter in YMM10=0D ;=0D @@ -455,14 +472,47 @@ ASM_PFX(TempRamInitApi): ParamValid:=0D SAVE_RCX=0D =0D + mov rdx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize))=0D + mov edx, DWORD [rdx]=0D ;=0D - ; Save timestamp into YMM6=0D + ; Read ARCH2 UPD input value.=0D ;=0D - rdtsc=0D - shl rdx, 32=0D - or rax, rdx=0D - SAVE_TS rax=0D + mov ebx, DWORD [ecx + LoadMicrocodeParamsFsp24.FspTemporaryRamSize= ]=0D + ;=0D + ; As per spec, if Bootloader pass zero, use Fsp defined Size=0D + ; Irrespective of whether this UPD is supported or not, Fallback=0D + ; to Fsp defined size if input is zero.=0D + ;=0D + cmp ebx, 0=0D + jz UseTemporaryRamSizePcd=0D +=0D + xor rax, rax=0D + mov ax, WORD [rsi + 020h] ; Read ImageAttribute=0D + test ax, 16 ; check if Bit4 is set=0D + jnz ConsumeInputConfiguration=0D + ;=0D + ; Sometimes user may change input value even if it is not supported=0D + ; return error if input is Non-Zero and not same as PcdTemporaryRamSize.= =0D + ;=0D + cmp ebx, edx=0D + je UseTemporaryRamSizePcd=0D + mov rax, 08000000000000002h ; RETURN_INVALID_PARAMETER=0D + jmp TempRamInitExit=0D +ConsumeInputConfiguration:=0D + ;=0D + ; Read Fsp Arch2 revision=0D + cmp byte [ecx + LoadMicrocodeParamsFsp24.FsptArchRevision], 3=0D + jb UseTemporaryRamSizePcd=0D + ;=0D + ; Read ARCH2 UPD value and Save.=0D + ; Only low-32 bits of rbx/rdx holds the temporary ram size.=0D + ;=0D + SAVE_TEMPORARY_RAM_SIZE rbx=0D + jmp GotTemporaryRamSize=0D +UseTemporaryRamSizePcd:=0D + SAVE_TEMPORARY_RAM_SIZE rdx=0D =0D +GotTemporaryRamSize:=0D ;=0D ; Sec Platform Init=0D ;=0D diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Include/Fs= pEas/FspApi.h index 40e063e944..27d5ec3a3c 100644 --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -139,7 +139,7 @@ typedef struct { ///=0D typedef struct {=0D ///=0D - /// Revision of the structure is 2 for this version of the specification= .=0D + /// Revision of the structure is 3 for this version of the specification= .=0D ///=0D UINT8 Revision;=0D UINT8 Reserved[3];=0D @@ -152,7 +152,8 @@ typedef struct { /// occurring during FSP execution.=0D ///=0D EFI_PHYSICAL_ADDRESS FspDebugHandler;=0D - UINT8 Reserved1[16];=0D + UINT32 FspTemporaryRamSize;=0D + UINT8 Reserved1[12];=0D } FSPT_ARCH2_UPD;=0D =0D ///=0D diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc b/IntelFsp2Pkg/= Include/SaveRestoreSseAvxNasm.inc index 002a5a1412..2168564e6d 100644 --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc @@ -201,6 +201,27 @@ movq rcx, xmm5=0D %endmacro=0D =0D +;=0D +; Save TemporaryRamSize to YMM10[192:255]=0D +; arg 1:general purpose register which holds TemporaryRamSize=0D +; Modified: XMM5 and YMM10[192:255]=0D +;=0D +%macro SAVE_TEMPORARY_RAM_SIZE 1=0D + LYMMN ymm10, xmm5, 1=0D + SXMMN xmm5, 1, %1=0D + SYMMN ymm10, 1, xmm5=0D + %endmacro=0D +=0D +;=0D +; Restore TemporaryRamSize from YMM10[192:255]=0D +; arg 1:general purpose register where to save TemporaryRamSize=0D +; Modified: XMM5 and %1=0D +;=0D +%macro LOAD_TEMPORARY_RAM_SIZE 1=0D + LYMMN ymm10, xmm5, 1=0D + LXMMN xmm5, %1, 1=0D + %endmacro=0D +=0D ;=0D ; YMM7[128:191] for calling stack=0D ; arg 1:Entry=0D diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec index d1c3d3ee7b..426d31a13f 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dec +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec @@ -85,6 +85,11 @@ gFspEventEndOfFirmwareGuid =3D { 0xbd44f629, 0xeae7, 0x4198, = { 0x87, 0xf1, 0x39, 0xfa, 0xb0, 0xfd, 0x71, 0x7e } }=0D =0D [PcdsFixedAtBuild]=0D + #=0D + # As part of FSP-T execution, this will be initialized to TemporaryRamSi= ze that FSP-T used =0D + # for TemporaryRam configuraiton.Once Fsp Global Data is initialed later= in FSP-M, this =0D + # will hold the Global data buffer address.=0D + #=0D gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress |0xFED00108|UINT= 32|0x00000001=0D gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase |0xFEF00000|UINT= 32|0x10001001=0D gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize | 0x2000|UINT= 32|0x10001002=0D diff --git a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/= SecRamInitData.c b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibS= ample/SecRamInitData.c index fb0d9a8683..316c2fa86a 100644 --- a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamI= nitData.c +++ b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/SecRamI= nitData.c @@ -49,8 +49,9 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA F= sptUpdDataPtr =3D { },=0D 0x00000020,=0D 0x00000000,=0D + 0x00000000,=0D {=0D - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D }=0D },=0D --=20 2.39.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#116097): https://edk2.groups.io/g/devel/message/116097 Mute This Topic: https://groups.io/mt/104620019/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-