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Wed, 11 Jan 2023 00:17:07 -0600 From: "Abdul Lateef Attar" To: CC: Abdul Lateef Attar , Paul Grimes , Garrett Kirkendall , Abner Chang , Eric Dong , Ray Ni , Rahul Kumar Subject: [PATCH v2 5/6] UefiCpuPkg: Initial implementation of AMD's SmmCpuFeaturesLib Date: Wed, 11 Jan 2023 11:45:43 +0530 Message-ID: <606bd9523bc41116e845066c788185941518976a.1673417268.git.abdattar@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Return-Path: AbdulLateef.Attar@amd.com X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT052:EE_|DM4PR12MB6182:EE_ X-MS-Office365-Filtering-Correlation-Id: 39779b8c-2531-4c3d-f8ac-08daf39b8ba2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gFjhlRnF+PYU/DRVLceGL4T9KMpKy1n6RLBAW/F1NnNOUh99Gx2wk9k5sD26lPuk5xJr3hEDF6/bs/4LP7s0pIBJijs6fBK839+IpzNuTSQjUZug/iOQXaP9gN74FcnGIfLwbC6NoDMbws7kIQMemk08mtNfosF5yuqwUXfNHdwNdvTVsvFa0n2YkPrzzyQM3MRcbZrrj/UN1Q3LFKmyGdqlon+IoAdPsw85jyue3hhFts20IVHewfc7l5lm1TucXQGIun6IngA5c+D2+d8W+Wnmry5eI8Km4562qmXJFDOfjON6HaJl0GdL9h8xf+KBul8/hmRloHed3u1C+j/oideRL+p0bwzGt5rVYkRSKjCRaGtVJJjblrYzllwmvfkxdsrVtLOZFtEA1xLiO/4HC7M4sjAnpXGg3mAVf1MDgNM3mfu/BOoTdqhifyT0hXS/kx3CL6td2DcNUPt5B46giYbqfJjp/QFaIuo99yDbPpIR3pMOiTS7xp1a76xACVqK/u/JEoqDmaieKhWny808ylaMdOk3Tb89JNLql6CeLbY0E+80Per05dvAMA+ZGtE53gMZWl3WRlXgTX8S+moAOOP2mJQBPYZ4meW2KkEkDkzzwf+vyyY1+OedFBtF9hUthbBCsv5S3ghokdaUHbcfMuIkv/QKvIFv2x/BApj/4bCnBn4rzNUUKEpe5btIfpoZreNgXd5Wh/P6BFqh09JU0dwpZeQbdEZxRwwwRMdtaojU069z26iQUMsJPR6E4l+OgHuJHaeXUqMLdhC8l9qiNw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(396003)(376002)(346002)(39860400002)(451199015)(36840700001)(40470700004)(46966006)(356005)(81166007)(82740400003)(36860700001)(70206006)(45080400002)(4326008)(70586007)(41300700001)(40460700003)(6916009)(54906003)(8676002)(316002)(40480700001)(8936002)(5660300002)(2906002)(30864003)(2616005)(336012)(83380400001)(47076005)(426003)(7696005)(82310400005)(966005)(186003)(6666004)(26005)(19627235002)(478600001)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jan 2023 06:17:41.4071 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39779b8c-2531-4c3d-f8ac-08daf39b8ba2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT052.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6182 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Abdul Lateef Attar BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4182 Adds initial defination for AMD's SmmCpuFeaturesLib library implementation. All function's body either empty or just returns value. Its initial skeleton of library implementation. Cc: Paul Grimes Cc: Garrett Kirkendall Cc: Abner Chang Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Abdul Lateef Attar --- UefiCpuPkg/UefiCpuPkg.dsc | 8 + .../AmdSmmCpuFeaturesLib.inf | 33 ++ .../SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c | 345 ++++++++++++++++++ 3 files changed, 386 insertions(+) create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesL= ib.inf create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeatures= Lib.c diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 99f7532ce00b..1833d35fb354 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -178,6 +178,13 @@ [Components.IA32, Components.X64] =0D SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeature= sLibStm.inf=0D }=0D + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf {=0D + =0D + FILE_GUID =3D B7242C74-BD21-49EE-84B4-07162E8C080D=0D + =0D + SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeat= uresLib.inf=0D + SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/S= mmCpuPlatformHookLibNull.inf=0D + }=0D UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf=0D UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf=0D UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf=0D @@ -194,6 +201,7 @@ [Components.IA32, Components.X64] UnitTestResultReportLib|UnitTestFrameworkPkg/Library/UnitTestResultR= eportLib/UnitTestResultReportLibConOut.inf=0D }=0D UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmmSmramSaveStateLib.inf=0D + UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf=0D =0D [Components.X64]=0D UefiCpuPkg/Library/CpuExceptionHandlerLib/UnitTest/DxeCpuExceptionHandle= rLibUnitTest.inf=0D diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf = b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf new file mode 100644 index 000000000000..547b9cf15b84 --- /dev/null +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf @@ -0,0 +1,33 @@ +## @file=0D +# The CPU specific programming for PiSmmCpuDxeSmm module.=0D +#=0D +# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
= =0D +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D SmmCpuFeaturesLib=0D + MODULE_UNI_FILE =3D SmmCpuFeaturesLib.uni=0D + FILE_GUID =3D 5849E964-78EC-428E-8CBD-848A7E359134= =0D + MODULE_TYPE =3D DXE_SMM_DRIVER=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D SmmCpuFeaturesLib=0D + CONSTRUCTOR =3D SmmCpuFeaturesLibConstructor=0D +=0D +[Sources]=0D + SmmCpuFeaturesLib.c=0D + SmmCpuFeaturesLibCommon.c=0D + Amd/SmmCpuFeaturesLib.c=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + UefiCpuPkg/UefiCpuPkg.dec=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + PcdLib=0D + MemoryAllocationLib=0D + DebugLib=0D diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c b= /UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c new file mode 100644 index 000000000000..c74e1a0c0c5b --- /dev/null +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c @@ -0,0 +1,345 @@ +/** @file=0D +Implementation specific to the SmmCpuFeatureLib library instance=0D +for AMD based platforms.=0D +=0D +Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
=0D +Copyright (c) Microsoft Corporation.
=0D +Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +=0D +/**=0D + Read an SMM Save State register on the target processor. If this functi= on=0D + returns EFI_UNSUPPORTED, then the caller is responsible for reading the= =0D + SMM Save Sate register.=0D +=0D + @param[in] CpuIndex The index of the CPU to read the SMM Save State. = The=0D + value must be between 0 and the NumberOfCpus field= in=0D + the System Management System Table (SMST).=0D + @param[in] Register The SMM Save State register to read.=0D + @param[in] Width The number of bytes to read from the CPU save stat= e.=0D + @param[out] Buffer Upon return, this holds the CPU register value rea= d=0D + from the save state.=0D +=0D + @retval EFI_SUCCESS The register was read from Save State.=0D + @retval EFI_INVALID_PARAMTER Buffer is NULL.=0D + @retval EFI_UNSUPPORTED This function does not support reading Reg= ister.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SmmCpuFeaturesReadSaveStateRegister (=0D + IN UINTN CpuIndex,=0D + IN EFI_SMM_SAVE_STATE_REGISTER Register,=0D + IN UINTN Width,=0D + OUT VOID *Buffer=0D + )=0D +{=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Writes an SMM Save State register on the target processor. If this func= tion=0D + returns EFI_UNSUPPORTED, then the caller is responsible for writing the= =0D + SMM Save Sate register.=0D +=0D + @param[in] CpuIndex The index of the CPU to write the SMM Save State. = The=0D + value must be between 0 and the NumberOfCpus field = in=0D + the System Management System Table (SMST).=0D + @param[in] Register The SMM Save State register to write.=0D + @param[in] Width The number of bytes to write to the CPU save state.= =0D + @param[in] Buffer Upon entry, this holds the new CPU register value.= =0D +=0D + @retval EFI_SUCCESS The register was written to Save State.=0D + @retval EFI_INVALID_PARAMTER Buffer is NULL.=0D + @retval EFI_UNSUPPORTED This function does not support writing Reg= ister.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SmmCpuFeaturesWriteSaveStateRegister (=0D + IN UINTN CpuIndex,=0D + IN EFI_SMM_SAVE_STATE_REGISTER Register,=0D + IN UINTN Width,=0D + IN CONST VOID *Buffer=0D + )=0D +{=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Performs library initialization.=0D +=0D + This initialization function contains common functionality shared betwen= all=0D + library instance constructors.=0D +=0D +**/=0D +VOID=0D +CpuFeaturesLibInitialization (=0D + VOID=0D + )=0D +{=0D +}=0D +=0D +/**=0D + Called during the very first SMI into System Management Mode to initiali= ze=0D + CPU features, including SMBASE, for the currently executing CPU. Since = this=0D + is the first SMI, the SMRAM Save State Map is at the default address of= =0D + AMD_SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently exe= cuting=0D + CPU is specified by CpuIndex and CpuIndex can be used to access informat= ion=0D + about the currently executing CPU in the ProcessorInfo array and the=0D + HotPlugCpuData data structure.=0D +=0D + @param[in] CpuIndex The index of the CPU to initialize. The valu= e=0D + must be between 0 and the NumberOfCpus field = in=0D + the System Management System Table (SMST).=0D + @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU = that=0D + was elected as monarch during System Manageme= nt=0D + Mode initialization.=0D + FALSE if the CpuIndex is not the index of the= CPU=0D + that was elected as monarch during System=0D + Management Mode initialization.=0D + @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMAT= ION=0D + structures. ProcessorInfo[CpuIndex] contains= the=0D + information for the currently executing CPU.= =0D + @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure th= at=0D + contains the ApidId and SmBase arrays.=0D +**/=0D +VOID=0D +EFIAPI=0D +SmmCpuFeaturesInitializeProcessor (=0D + IN UINTN CpuIndex,=0D + IN BOOLEAN IsMonarch,=0D + IN EFI_PROCESSOR_INFORMATION *ProcessorInfo,=0D + IN CPU_HOT_PLUG_DATA *CpuHotPlugData=0D + )=0D +{=0D +}=0D +=0D +/**=0D + This function updates the SMRAM save state on the currently executing CP= U=0D + to resume execution at a specific address after an RSM instruction. Thi= s=0D + function must evaluate the SMRAM save state to determine the execution m= ode=0D + the RSM instruction resumes and update the resume execution address with= =0D + either NewInstructionPointer32 or NewInstructionPoint. The auto HALT re= start=0D + flag in the SMRAM save state must always be cleared. This function retu= rns=0D + the value of the instruction pointer from the SMRAM save state that was= =0D + replaced. If this function returns 0, then the SMRAM save state was not= =0D + modified.=0D +=0D + This function is called during the very first SMI on each CPU after=0D + SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mo= de=0D + to signal that the SMBASE of each CPU has been updated before the defaul= t=0D + SMBASE address is used for the first SMI to the next CPU.=0D +=0D + @param[in] CpuIndex The index of the CPU to hook. The v= alue=0D + must be between 0 and the NumberOfCp= us=0D + field in the System Management Syste= m Table=0D + (SMST).=0D + @param[in] CpuState Pointer to SMRAM Save State Map for = the=0D + currently executing CPU.=0D + @param[in] NewInstructionPointer32 Instruction pointer to use if resumi= ng to=0D + 32-bit execution mode from 64-bit SM= M.=0D + @param[in] NewInstructionPointer Instruction pointer to use if resumi= ng to=0D + same execution mode as SMM.=0D +=0D + @retval 0 This function did modify the SMRAM save state.=0D + @retval > 0 The original instruction pointer value from the SMRAM save = state=0D + before it was replaced.=0D +**/=0D +UINT64=0D +EFIAPI=0D +SmmCpuFeaturesHookReturnFromSmm (=0D + IN UINTN CpuIndex,=0D + IN SMRAM_SAVE_STATE_MAP *CpuState,=0D + IN UINT64 NewInstructionPointer32,=0D + IN UINT64 NewInstructionPointer=0D + )=0D +{=0D + return 0;=0D +}=0D +=0D +/**=0D + Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is=0D + returned, then a custom SMI handler is not provided by this library,=0D + and the default SMI handler must be used.=0D +=0D + @retval 0 Use the default SMI handler.=0D + @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHa= ndler()=0D + The caller is required to allocate enough SMRAM for each CP= U to=0D + support the size of the custom SMI handler.=0D +**/=0D +UINTN=0D +EFIAPI=0D +SmmCpuFeaturesGetSmiHandlerSize (=0D + VOID=0D + )=0D +{=0D + return 0;=0D +}=0D +=0D +/**=0D + Install a custom SMI handler for the CPU specified by CpuIndex. This fu= nction=0D + is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is gr= eater=0D + than zero and is called by the CPU that was elected as monarch during Sy= stem=0D + Management Mode initialization.=0D +=0D + @param[in] CpuIndex The index of the CPU to install the custom SMI han= dler.=0D + The value must be between 0 and the NumberOfCpus f= ield=0D + in the System Management System Table (SMST).=0D + @param[in] SmBase The SMBASE address for the CPU specified by CpuInd= ex.=0D + @param[in] SmiStack The stack to use when an SMI is processed by the=0D + the CPU specified by CpuIndex.=0D + @param[in] StackSize The size, in bytes, if the stack used when an SMI = is=0D + processed by the CPU specified by CpuIndex.=0D + @param[in] GdtBase The base address of the GDT to use when an SMI is= =0D + processed by the CPU specified by CpuIndex.=0D + @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is= =0D + processed by the CPU specified by CpuIndex.=0D + @param[in] IdtBase The base address of the IDT to use when an SMI is= =0D + processed by the CPU specified by CpuIndex.=0D + @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is= =0D + processed by the CPU specified by CpuIndex.=0D + @param[in] Cr3 The base address of the page tables to use when an= SMI=0D + is processed by the CPU specified by CpuIndex.=0D +**/=0D +VOID=0D +EFIAPI=0D +SmmCpuFeaturesInstallSmiHandler (=0D + IN UINTN CpuIndex,=0D + IN UINT32 SmBase,=0D + IN VOID *SmiStack,=0D + IN UINTN StackSize,=0D + IN UINTN GdtBase,=0D + IN UINTN GdtSize,=0D + IN UINTN IdtBase,=0D + IN UINTN IdtSize,=0D + IN UINT32 Cr3=0D + )=0D +{=0D +}=0D +=0D +/**=0D + Determines if MTRR registers must be configured to set SMRAM cache-abili= ty=0D + when executing in System Management Mode.=0D +=0D + @retval TRUE MTRR registers must be configured to set SMRAM cache-abil= ity.=0D + @retval FALSE MTRR registers do not need to be configured to set SMRAM= =0D + cache-ability.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +SmmCpuFeaturesNeedConfigureMtrrs (=0D + VOID=0D + )=0D +{=0D + return FALSE;=0D +}=0D +=0D +/**=0D + Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigu= reMtrrs()=0D + returns TRUE.=0D +**/=0D +VOID=0D +EFIAPI=0D +SmmCpuFeaturesDisableSmrr (=0D + VOID=0D + )=0D +{=0D +}=0D +=0D +/**=0D + Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigur= eMtrrs()=0D + returns TRUE.=0D +**/=0D +VOID=0D +EFIAPI=0D +SmmCpuFeaturesReenableSmrr (=0D + VOID=0D + )=0D +{=0D +}=0D +=0D +/**=0D + Processor specific hook point each time a CPU enters System Management M= ode.=0D +=0D + @param[in] CpuIndex The index of the CPU that has entered SMM. The val= ue=0D + must be between 0 and the NumberOfCpus field in the= =0D + System Management System Table (SMST).=0D +**/=0D +VOID=0D +EFIAPI=0D +SmmCpuFeaturesRendezvousEntry (=0D + IN UINTN CpuIndex=0D + )=0D +{=0D +}=0D +=0D +/**=0D + Returns the current value of the SMM register for the specified CPU.=0D + If the SMM register is not supported, then 0 is returned.=0D +=0D + @param[in] CpuIndex The index of the CPU to read the SMM register. The= =0D + value must be between 0 and the NumberOfCpus field = in=0D + the System Management System Table (SMST).=0D + @param[in] RegName Identifies the SMM register to read.=0D +=0D + @return The value of the SMM register specified by RegName from the CPU= =0D + specified by CpuIndex.=0D +**/=0D +UINT64=0D +EFIAPI=0D +SmmCpuFeaturesGetSmmRegister (=0D + IN UINTN CpuIndex,=0D + IN SMM_REG_NAME RegName=0D + )=0D +{=0D + return 0;=0D +}=0D +=0D +/**=0D + Sets the value of an SMM register on a specified CPU.=0D + If the SMM register is not supported, then no action is performed.=0D +=0D + @param[in] CpuIndex The index of the CPU to write the SMM register. Th= e=0D + value must be between 0 and the NumberOfCpus field = in=0D + the System Management System Table (SMST).=0D + @param[in] RegName Identifies the SMM register to write.=0D + registers are read-only.=0D + @param[in] Value The value to write to the SMM register.=0D +**/=0D +VOID=0D +EFIAPI=0D +SmmCpuFeaturesSetSmmRegister (=0D + IN UINTN CpuIndex,=0D + IN SMM_REG_NAME RegName,=0D + IN UINT64 Value=0D + )=0D +{=0D +}=0D +=0D +/**=0D + Check to see if an SMM register is supported by a specified CPU.=0D +=0D + @param[in] CpuIndex The index of the CPU to check for SMM register supp= ort.=0D + The value must be between 0 and the NumberOfCpus fi= eld=0D + in the System Management System Table (SMST).=0D + @param[in] RegName Identifies the SMM register to check for support.=0D +=0D + @retval TRUE The SMM register specified by RegName is supported by the= CPU=0D + specified by CpuIndex.=0D + @retval FALSE The SMM register specified by RegName is not supported by= the=0D + CPU specified by CpuIndex.=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +SmmCpuFeaturesIsSmmRegisterSupported (=0D + IN UINTN CpuIndex,=0D + IN SMM_REG_NAME RegName=0D + )=0D +{=0D + return FALSE;=0D +}=0D --=20 2.25.1