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Fri, 17 Mar 2023 01:50:21 -0500 From: "Abdul Lateef Attar" To: CC: Abdul Lateef Attar , Ard Biesheuvel , Leif Lindholm , Abner Chang , Michael D Kinney Subject: [PATCH v2 RESEND 3/4] Platform/AMD/BoarkPkg: Adds SetCacheMtrrLib library Date: Fri, 17 Mar 2023 12:20:06 +0530 Message-ID: <60ddb8be3b32bc6ff9745a51eef1f857c428a0f4.1679035605.git.abdattar@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Return-Path: AbdulLateef.Attar@amd.com X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT029:EE_|SJ2PR12MB9007:EE_ X-MS-Office365-Filtering-Correlation-Id: 9acf3261-d316-458a-5523-08db26b3e2b2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xHLQon1YnmxocGm/qdq3hTX1xDczVUlhggP6xyQOnbBRgnCE8ihqJIhDPLgmvbrc+V5SweOL67L/g5RQc8MPyrOFQ9wggqErwNGF9piHo0FEQhVFx0ticBnfW4d6uTLB8ylk8Tn8cVZtQ0ysi9RCC7/xdEmW1fHUHiWgsAOLZ5ijUJ/BfLxYfwLVDqVp3FyY65+30p0pgSAA/HxOr+Off2121n00k6MVdyGPWCz6quOvpPV7+FxL1L2hIepvM8onJBvQ0pw2SD0GVfRSwEO2m8lDfyjTedem5dKXdqJH4BpgQ9IAEV1EpY9BpiutrAJsl0F/7RWHaIKTJW3WiG4Y1Ji9nbWB1se11rF5f9NvF6IdLxlKemZtW5xMhu3pHTjAMRFcTIFMJ3xp91qNE2G5zj0uRsOhvn2Gv/lkWIsmjJmuaLW+mSsnBcQ1Z//dglRHDNI0VdT4fLPQcCDrLo2ip2lYKZlsyp5RfBRoOM0HcN/MO2ckSxWtg/PWNa+5k2PsttWb69cK8w7Z6/E9ap9OoExCxQN09EebZacMQV6KW2Fk4ePsugQSIJ/M2qMZ9zez4GnJpoj2U4uJKjJkrGj66OzQE1jvCYmR4TegxNsDkhwamlP2JCxb1oO2tsSdYUKwtQGf2TEi2iyT2iBFRACJNVnsALWHGh+BQnwV+p4Bp5V55uqRXYo6zd7bfua2hP3ftSOXwRm+A1drXMnFm0fZJchBjjbzyReGiDxKIUfiIVk= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(39860400002)(346002)(396003)(376002)(136003)(451199018)(46966006)(40470700004)(36840700001)(83380400001)(40460700003)(36756003)(40480700001)(82740400003)(81166007)(82310400005)(36860700001)(47076005)(26005)(186003)(356005)(2616005)(336012)(426003)(6666004)(478600001)(4326008)(7696005)(316002)(54906003)(8676002)(70586007)(6916009)(70206006)(41300700001)(8936002)(2906002)(5660300002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2023 06:50:24.6615 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9acf3261-d316-458a-5523-08db26b3e2b2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9007 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain Adds SetCacheMtrrLib library for AMD processor based boards. This library sets MTRR value or various memory ranges. Signed-off-by: Abdul Lateef Attar Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Abner Chang Cc: Michael D Kinney --- Platform/AMD/BoardPkg/BoardPkg.dsc | 10 ++ .../SetCacheMtrrLib/SetCacheMtrrLib.inf | 37 +++++ .../Library/SetCacheMtrrLib/SetCacheMtrrLib.c | 132 ++++++++++++++++++ 3 files changed, 179 insertions(+) create mode 100644 Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheM= trrLib.inf create mode 100644 Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheM= trrLib.c diff --git a/Platform/AMD/BoardPkg/BoardPkg.dsc b/Platform/AMD/BoardPkg/Boa= rdPkg.dsc index cb4065b86c60..aa0ee8287cd8 100644 --- a/Platform/AMD/BoardPkg/BoardPkg.dsc +++ b/Platform/AMD/BoardPkg/BoardPkg.dsc @@ -18,3 +18,13 @@ [Defines] =20 [Packages] BoardPkg/BoardPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses.common.PEIM] + SetCacheMtrrLib|BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf + +[Components.IA32] + BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf + diff --git a/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.= inf b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf new file mode 100644 index 000000000000..c66661d3f8dc --- /dev/null +++ b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf @@ -0,0 +1,37 @@ +## @file +# Component information file for Platform SetCacheMtrr Library. +# This library implementation is for AMD processor based platforms. +# +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 1.29 + BASE_NAME =3D PeiSetCacheMtrrLib + FILE_GUID =3D 1E8468E0-5EB4-4088-9B52-BFDC6E4DAE87 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SetCacheMtrrLib + +[LibraryClasses] + BaseLib + DebugLib + MtrrLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[Sources] + SetCacheMtrrLib.c + +[Guids] + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize + diff --git a/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.= c b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c new file mode 100644 index 000000000000..18404405d9fa --- /dev/null +++ b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c @@ -0,0 +1,132 @@ +/** @file + +SetCacheMtrr library functions. +This library implementation is for AMD processor based platforms. + +Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +/** + This function sets the cache MTRR values for PEI phase. +**/ +VOID +EFIAPI +SetCacheMtrr ( + VOID + ) +{ + EFI_STATUS Status; + + Status =3D MtrrSetMemoryAttribute ( + 0, + 0xA0000, + CacheWriteBack + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheWriteBack for 0-0x9FFFF\n", + Status + )); + } + + Status =3D MtrrSetMemoryAttribute ( + 0xA0000, + 0x20000, + CacheUncacheable + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheUncacheable for 0xA0000-0xBFFFF\n", + Status + )); + } + + Status =3D MtrrSetMemoryAttribute ( + 0xC0000, + 0x40000, + CacheWriteProtected + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheWriteProtected for 0xC0000-0xFFFFF\n", + Status + )); + } + + Status =3D MtrrSetMemoryAttribute ( + 0x100000, + 0xAFF00000, + CacheWriteBack + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheWriteBack for 0x100000-0xAFFFFFFF\n", + Status + )); + } + + Status =3D MtrrSetMemoryAttribute ( + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaSize), + CacheWriteProtected + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheWriteProtected for 0x%X-0x%X\n", + Status, + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaBaseAddress) + PcdGet32 (PcdFlashAreaSize) + )); + } + + MtrrDebugPrintAllMtrrs (); + return; +} + +/** + Update MTRR setting in EndOfPei phase. + This function will set the MTRR value as CacheUncacheable + for Flash address. + + @retval EFI_SUCCESS The function completes successfully. + @retval Others Some error occurs. +**/ +EFI_STATUS +EFIAPI +SetCacheMtrrAfterEndOfPei ( + VOID + ) +{ + EFI_STATUS Status; + + Status =3D MtrrSetMemoryAttribute ( + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaSize), + CacheUncacheable + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheUncacheable for 0x%X-0x%X\n", + Status, + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaBaseAddress) + PcdGet32 (PcdFlashAreaSize) + )); + } + + MtrrDebugPrintAllMtrrs (); + return EFI_SUCCESS; +} --=20 2.25.1