From: "Laszlo Ersek" <lersek@redhat.com>
To: devel@edk2.groups.io, wangxiao.bj@inspur.com,
"tigerliu@zhaoxin.com" <tigerliu@zhaoxin.com>
Subject: Re: 答复: [edk2-devel] question about PCI bridge's bus range window configure's save and restore
Date: Mon, 10 Aug 2020 23:32:37 +0200 [thread overview]
Message-ID: <62758fad-1ca3-e46d-7302-86742700981b@redhat.com> (raw)
In-Reply-To: <0f1b74aaf0774f25bfd76d476a05b598@inspur.com>
On 08/10/20 13:54, Ric Wang (王晓) wrote:
> It’s done by BIOS pei s3 resume code. Restored register value saved while BIOS normal POST BY BootScriptExecutor. You can refer gEfiPeiS3Resume2Ppi usage
That doesn't seem right. The S3 boot script is composed by platform
drivers in the firmware, for restoring platform hardware state.
But the registers in question, in PCI config space, are specified in the
PCI(e) spec(s), and the OS is virtually guaranteed to have drivers for
PCI bridges / PCIe ports. The OS may even re-enumerate the PCI hierarchy
(overriding what the firmware put in place), after which restoring the
same configuration in the firmware, during S3 resume, would be wrong.
Considering edk2, because PciBusDxe sets the bus numbers initially
(possibly influenced by the platform's EFI_PCI_HOT_PLUG_INIT_PROTOCOL
provider), if S3 boot script opcodes were saved for this, we should see
PciBusDxe consume "gEfiS3SaveStateProtocolGuid". But it doesn't.
If at S3, the port goes into D3hot state or shallower, then its config
space is not lost. If the port goes into D3, then the OS knows it has to
reprogram it after resume. That's my (very superficial) understanding
anyway, from the ACPI spec.
The Linux kernel seems to have a lot of logic around "bridge_d3" under
"drivers/pci/".
Thanks
Laszlo
> Thanks
>
> 发件人: devel@edk2.groups.io [mailto:devel@edk2.groups.io] 代表 Tiger Liu(BJ-RD)
> 发送时间: 2020年8月10日 17:32
> 收件人: devel@edk2.groups.io
> 主题: [edk2-devel] question about PCI bridge's bus range window configure's save and restore
>
>
>
> Hi, Experts:
>
> I have a question about PCI Bridge’s config space’s save and restore.
>
>
>
> Pci bus driver configured PCI Bridges’ secondary bus number register and subordinate bus number register.
>
>
>
> So, if system resumes from S3(Suspend to ram) state, who is responsible for restoring PCI Bridges’ secondary bus number / subordinate bus number registers’ content?
>
>
>
> Will the OS be responsible for it?
>
>
>
> Thanks
>
>
>
>
>
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next prev parent reply other threads:[~2020-08-10 21:32 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-10 9:31 [edk2-devel] question about PCI bridge's bus range window configure's save and restore Tiger Liu(BJ-RD)
2020-08-10 11:54 ` 答复: " wangxiao.bj
2020-08-10 21:32 ` Laszlo Ersek [this message]
2020-08-11 2:09 ` Feng Libo
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