From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.zytor.com (terminus.zytor.com [65.50.211.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AE1AE21967BD7 for ; Tue, 6 Jun 2017 12:42:53 -0700 (PDT) Received: from tazenda.hos.anvin.org (c-24-5-245-234.hsd1.ca.comcast.net [24.5.245.234] (may be forged)) (authenticated bits=0) by mail.zytor.com (8.15.2/8.15.2) with ESMTPSA id v56Jfl8W025324 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Tue, 6 Jun 2017 12:41:47 -0700 To: "Fan, Jeff" , "Kinney, Michael D" , "edk2-devel@lists.01.org" Cc: Andrew Fish References: <1495473154-18184-1-git-send-email-michael.d.kinney@intel.com> <542CF652F8836A4AB8DBFAAD40ED192A4C5E8084@shsmsx102.ccr.corp.intel.com> From: "H. Peter Anvin" Message-ID: <629c1154-77c8-07cf-131e-cdc64300245c@zytor.com> Date: Tue, 6 Jun 2017 12:41:42 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.0 MIME-Version: 1.0 In-Reply-To: <542CF652F8836A4AB8DBFAAD40ED192A4C5E8084@shsmsx102.ccr.corp.intel.com> Subject: Re: [Patch V2] UefiCpuPkg/MpInitLib: Fix X64 XCODE5/NASM compatibility issues X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Jun 2017 19:42:53 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 05/22/17 19:08, Fan, Jeff wrote: > > diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm > index fa54d01..0b14a53 100644 > --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm > +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm > @@ -1,5 +1,5 @@ > ;------------------------------------------------------------------------------ ; -; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
> +; Copyright (c) 2015 - 2017, Intel Corporation. All rights > +reserved.
> ; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BSD License ; which accompanies this distribution. The full text of the license may be found at @@ -201,7 +201,7 @@ CProcedureInvoke: > push rbp > mov rbp, rsp > > - mov rax, ASM_PFX(InitializeFloatingPointUnits) > + mov rax, qword [esi + InitializeFloatingPointUnitsAddress] > sub rsp, 20h > call rax ; Call assembly function to initialize FPU per UEFI spec > add rsp, 20h FYI, the qword specifier is unnecessary since you are already specifying rax. However, why not simply drop the use of rax entirely and do: call [esi + InitializeFloatingPointUnitsAddress] (Also: is this *really* supposed to be esi and not rsi? The former means a 32-bit address.) -hpa