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contact devel+owner@edk2.groups.io Resent-Date: Sun, 31 Mar 2024 05:03:13 -0700 Reply-To: devel@edk2.groups.io,sami.mujawar@arm.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: IwffjfX0Hj5i6nd3ET7xlWECx7686176AA= Content-Language: en-GB Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=tvsaAI4t; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=arm.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Hi Prabin, Thank you for this patch. These changes look good to me. Reviewed-by: Sami Mujawar Regards, Sami Mujawar On 11/03/2024 01:14 pm, Prabin CA wrote: > From: Shriram K > > RD-Fremont is the next platform in the Arm's reference design platform > series. This platform includes 32 CPUs but the fixed virtual platform > (FVP) simulates 16 CPUs of the platform. There is one CPU per cluster in > the system and so the FVP simulates 16 clusters. In preparation for > adding support for this platform, add the initial set of ACPI tables and > reuse existing ACPI tables as applicable to boot a operating system on > this platform. > > Signed-off-by: Prabin CA > --- > Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf | 73 ++++++++ > Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl | 196 ++++++++++= ++++++++++ > Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc | 138 ++++++++++= ++++ > Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc | 167 ++++++++++= +++++++ > 4 files changed, 574 insertions(+) > > diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf b/Pla= tform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf > new file mode 100644 > index 000000000000..9d07001dec96 > --- /dev/null > +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremontAcpiTables.inf > @@ -0,0 +1,73 @@ > +## @file > +# ACPI table data and ASL sources required to boot the platform. > +# > +# Copyright (c) 2024, Arm Ltd. All rights reserved. > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x0001001A > + BASE_NAME =3D RdFremontAcpiTables > + FILE_GUID =3D c712719a-0aaf-438c-9cdd-35ab4d60207= d # gArmSgiAcpiTablesGuid > + MODULE_TYPE =3D USER_DEFINED > + VERSION_STRING =3D 1.0 > + > +[Sources] > + Dbg2.aslc > + Fadt.aslc > + Gtdt.aslc > + RdFremont/Dsdt.asl > + RdFremont/Madt.aslc > + RdFremont/Pptt.aslc > + Spcr.aslc > + SsdtEvents.asl > + SsdtRos.asl > + SsdtRosVirtioP9.asl > + > +[Packages] > + ArmPkg/ArmPkg.dec > + ArmPlatformPkg/ArmPlatformPkg.dec > + EmbeddedPkg/EmbeddedPkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + Platform/ARM/SgiPkg/SgiPlatform.dec > + > +[FixedPcd] > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase > + > + gArmPlatformTokenSpaceGuid.PcdSerialDbgInterrupt > + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase > + gArmPlatformTokenSpaceGuid.PL011UartInterrupt > + gArmPlatformTokenSpaceGuid.PcdCoreCount > + gArmPlatformTokenSpaceGuid.PcdClusterCount > + > + gArmSgiTokenSpaceGuid.PcdGpioController0BaseAddress > + gArmSgiTokenSpaceGuid.PcdGpioController0Size > + gArmSgiTokenSpaceGuid.PcdGpioController0Interrupt > + gArmSgiTokenSpaceGuid.PcdGtFrame0Gsiv > + gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv > + gArmSgiTokenSpaceGuid.PcdSp804DualTimerBaseAddress > + gArmSgiTokenSpaceGuid.PcdSp804DualTimerSize > + gArmSgiTokenSpaceGuid.PcdSp804DualTimerInterrupt > + gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress > + gArmSgiTokenSpaceGuid.PcdVirtioBlkSize > + gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt > + gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress > + gArmSgiTokenSpaceGuid.PcdVirtioNetSize > + gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt > + gArmSgiTokenSpaceGuid.PcdVirtioP9BaseAddress > + gArmSgiTokenSpaceGuid.PcdVirtioP9Size > + gArmSgiTokenSpaceGuid.PcdVirtioP9Interrupt > + gArmSgiTokenSpaceGuid.PcdWdogWS0Gsiv > + gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv > + > + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum > + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum > + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum > + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum > + gArmTokenSpaceGuid.PcdGicDistributorBase > + gArmTokenSpaceGuid.PcdGicRedistributorsBase > + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase > + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase > diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl b/Platform= /ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl > new file mode 100644 > index 000000000000..8812ea877f7a > --- /dev/null > +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Dsdt.asl > @@ -0,0 +1,196 @@ > +/** @file > +* Differentiated System Description Table Fields (DSDT) > +* > +* Copyright (c) 2024, Arm Limited. All rights reserved.
> +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +* @par Specification Reference: > +* - ACPI 6.5, Chapter 5, Section 5.2.11.1, Differentiated System Descr= iption > +* Table (DSDT) > +* > +**/ > + > +#include "SgiAcpiHeader.h" > +#include "SgiPlatform.h" > + > +DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARMSGI", > + EFI_ACPI_ARM_OEM_REVISION) { > + Scope (_SB) { > + Device (CL00) { // Cluster 0 > + Name (_HID, "ACPI0010") > + Name (_UID, 0) > + > + Device (CP00) { // Neoverse Poseidon core 0 > + Name (_HID, "ACPI0007") > + Name (_UID, 0) > + Name (_STA, 0xF) > + } > + } > + > + Device (CL01) { // Cluster 1 > + Name (_HID, "ACPI0010") > + Name (_UID, 1) > + > + Device (CP01) { // Neoverse Poseidon core 1 > + Name (_HID, "ACPI0007") > + Name (_UID, 1) > + Name (_STA, 0xF) > + } > + } > + > + Device (CL02) { // Cluster 2 > + Name (_HID, "ACPI0010") > + Name (_UID, 2) > + > + Device (CP02) { // Neoverse Poseidon core 2 > + Name (_HID, "ACPI0007") > + Name (_UID, 2) > + Name (_STA, 0xF) > + } > + } > + > + Device (CL03) { // Cluster 3 > + Name (_HID, "ACPI0010") > + Name (_UID, 3) > + > + Device (CP03) { // Neoverse Poseidon core 3 > + Name (_HID, "ACPI0007") > + Name (_UID, 3) > + Name (_STA, 0xF) > + } > + } > + > + Device (CL04) { // Cluster 4 > + Name (_HID, "ACPI0010") > + Name (_UID, 4) > + > + Device (CP04) { // Neoverse Poseidon core 4 > + Name (_HID, "ACPI0007") > + Name (_UID, 4) > + Name (_STA, 0xF) > + } > + } > + > + Device (CL05) { // Cluster 5 > + Name (_HID, "ACPI0010") > + Name (_UID, 5) > + > + Device (CP05) { // Neoverse Poseidon core 5 > + Name (_HID, "ACPI0007") > + Name (_UID, 5) > + Name (_STA, 0xF) > + } > + } > + > + Device (CL06) { // Cluster 6 > + Name (_HID, "ACPI0010") > + Name (_UID, 6) > + > + Device (CP06) { // Neoverse Poseidon core 6 > + Name (_HID, "ACPI0007") > + Name (_UID, 6) > + Name (_STA, 0xF) > + } > + } > + > + Device (CL07) { // Cluster 7 > + Name (_HID, "ACPI0010") > + Name (_UID, 7) > + > + Device (CP07) { // Neoverse Poseidon core 7 > + Name (_HID, "ACPI0007") > + Name (_UID, 7) > + Name (_STA, 0xF) > + } > + } > + > + Device (CL08) { // Cluster 8 > + Name (_HID, "ACPI0010") > + Name (_UID, 8) > + > + Device (CP08) { // Neoverse Poseidon core 8 > + Name (_HID, "ACPI0007") > + Name (_UID, 8) > + Name (_STA, 0xF) > + } > + } > + > + Device (CL09) { // Cluster 9 > + Name (_HID, "ACPI0010") > + Name (_UID, 9) > + > + Device (CP09) { // Neoverse Poseidon core 9 > + Name (_HID, "ACPI0007") > + Name (_UID, 9) > + Name (_STA, 0xF) > + } > + } > + > + Device (CL10) { // Cluster 10 > + Name (_HID, "ACPI0010") > + Name (_UID, 10) > + > + Device (CP10) { // Neoverse Poseidon core 10 > + Name (_HID, "ACPI0007") > + Name (_UID, 10) > + Name (_STA, 0xF) > + } > + } > + > + Device (CL11) { // Cluster 11 > + Name (_HID, "ACPI0010") > + Name (_UID, 11) > + > + Device (CP11) { // Neoverse Poseidon core 11 > + Name (_HID, "ACPI0007") > + Name (_UID, 11) > + Name (_STA, 0xF) > + } > + } > + > + Device (CL12) { // Cluster 12 > + Name (_HID, "ACPI0010") > + Name (_UID, 12) > + > + Device (CP12) { // Neoverse Poseidon core 12 > + Name (_HID, "ACPI0007") > + Name (_UID, 12) > + Name (_STA, 0xF) > + } > + } > + > + Device (CL13) { // Cluster 13 > + Name (_HID, "ACPI0010") > + Name (_UID, 13) > + > + Device (CP13) { // Neoverse Poseidon core 13 > + Name (_HID, "ACPI0007") > + Name (_UID, 13) > + Name (_STA, 0xF) > + } > + } > + > + Device (CL14) { // Cluster 14 > + Name (_HID, "ACPI0010") > + Name (_UID, 14) > + > + Device (CP14) { // Neoverse Poseidon core 14 > + Name (_HID, "ACPI0007") > + Name (_UID, 14) > + Name (_STA, 0xF) > + } > + } > + > + Device (CL15) { // Cluster 15 > + Name (_HID, "ACPI0010") > + Name (_UID, 15) > + > + Device (CP15) { // Neoverse Poseidon core 15 > + Name (_HID, "ACPI0007") > + Name (_UID, 15) > + Name (_STA, 0xF) > + } > + } > + } // Scope(_SB) > +} > diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc b/Platfor= m/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc > new file mode 100644 > index 000000000000..e81ce86ae8fd > --- /dev/null > +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Madt.aslc > @@ -0,0 +1,138 @@ > +/** @file > +* Multiple APIC Description Table (MADT) > +* > +* Copyright (c) 2024, Arm Limited. All rights reserved. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +**/ > + > +#include > +#include > +#include > + > +#include "SgiAcpiHeader.h" > +#include "SgiPlatform.h" > + > +#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \ > + FixedPcdGet32 (PcdCoreCount)) > + > +// Multiple APIC Description Table > +#pragma pack (1) > + > +typedef struct { > + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; > + EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[CO= RE_CNT]; > + EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; > + EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor= ; > + EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts[6]; > +} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE; > + > +#pragma pack () > + > +STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { > + { > + ARM_ACPI_HEADER ( > + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, > + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE, > + EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION > + ), > + // MADT specific fields > + 0, // LocalApicAddress > + 0 // Flags > + }, > + { > + // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr= , Flags, > + // PmuIrq, GicBase, GicVBas= e, > + // GicHBase, GsivId, GicRBa= se, > + // Efficiency, > + // SpeOverflowInterrupt) > + // Note: The GIC Structure of the primary CPU must be the first entr= y > + // (see note in 5.2.12.14 GICC Structure of ACPI v6.4). > + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core0 > + 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, > + FixedPcdGet32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0, 0, 0), > + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core1 > + 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, > + FixedPcdGet32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0, 0, 0), > + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core2 > + 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, > + FixedPcdGet32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0, 0, 0), > + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core3 > + 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, > + FixedPcdGet32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0, 0, 0), > + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core4 > + 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, > + FixedPcdGet32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0, 0, 0), > + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core5 > + 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, > + FixedPcdGet32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0, 0, 0), > + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core6 > + 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, > + FixedPcdGet32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0, 0, 0), > + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core7 > + 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, > + FixedPcdGet32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0, 0, 0), > + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core8 > + 0, 8, GET_MPID(0x800, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, > + FixedPcdGet32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0, 0, 0), > + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core9 > + 0, 9, GET_MPID(0x900, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, > + FixedPcdGet32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0, 0, 0), > + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core10 > + 0, 10, GET_MPID(0xa00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, > + FixedPcdGet32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0, 0, 0), > + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core11 > + 0, 11, GET_MPID(0xb00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, > + FixedPcdGet32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0, 0, 0), > + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core12 > + 0, 12, GET_MPID(0xc00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, > + FixedPcdGet32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0, 0, 0), > + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core13 > + 0, 13, GET_MPID(0xd00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, > + FixedPcdGet32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0, 0, 0), > + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core14 > + 0, 14, GET_MPID(0xe00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, > + FixedPcdGet32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0, 0, 0), > + EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Neoverse Poseidon core15 > + 0, 15, GET_MPID(0xf00, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23, > + FixedPcdGet32 (PcdGicDistributorBase), > + 0x2c020000, 0x2c010000, 25, 0, 0, 0), > + }, > + // GIC Distributor Entry > + EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorB= ase), > + 0, 3), > + // GIC Redistributor > + EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributor= sBase), > + SIZE_16MB), > + // GIC ITS > + { > + EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000), > + EFI_ACPI_6_4_GIC_ITS_INIT(1, 0x30080000), > + EFI_ACPI_6_4_GIC_ITS_INIT(2, 0x300C0000), > + EFI_ACPI_6_4_GIC_ITS_INIT(3, 0x30100000), > + EFI_ACPI_6_4_GIC_ITS_INIT(4, 0x30140000), > + EFI_ACPI_6_4_GIC_ITS_INIT(5, 0x30180000), > + }, > +}; > + > +// > +// Reference the table being generated to prevent the optimizer from rem= oving > +// the data structure from the executable > +// > +VOID* CONST ReferenceAcpiTable =3D &Madt; > diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc b/Platfor= m/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc > new file mode 100644 > index 000000000000..28cb6d452479 > --- /dev/null > +++ b/Platform/ARM/SgiPkg/AcpiTables/RdFremont/Pptt.aslc > @@ -0,0 +1,167 @@ > +/** @file > +* Processor Properties Topology Table (PPTT) for RD-Fremont platform > +* > +* Copyright (c) 2024, Arm Limited. All rights reserved. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +* This file describes the topological structure of the processor block o= n the > +* RD-Fremont platform in the form as defined by ACPI PPTT table. The RD-= Fremont > +* platform includes sixteen single-thread CPUs. Each of the CPUs include= 64KB > +* L1 Data cache, 64KB L1 Instruction cache and 2MB L2 cache. > +* > +* @par Specification Reference: > +* - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology= Table > +**/ > + > +#include > +#include > +#include > +#include > + > +#include "SgiAcpiHeader.h" > +#include "SgiPlatform.h" > + > +/** Define helper macro for populating processor core information. > + > + @param [in] PackageId Package instance number. > + @param [in] ClusterId Cluster instance number. > + @param [in] CpuId CPU instance number. > +**/ > +#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) = \ > + { = \ > + /* Parameters for CPU Core */ = \ > + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ > + OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ = \ > + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ = \ > + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ > + Package.Cluster[ClusterId]), /* Parent */ = \ > + ((PackageId << 4) | ClusterId), /* ACPI Id */ = \ > + 2 /* Num of private resource *= / \ > + ), = \ > + = \ > + /* Offsets of the private resources */ = \ > + { = \ > + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ > + Package.Cluster[ClusterId].Core[CpuId].DCache), = \ > + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ > + Package.Cluster[ClusterId].Core[CpuId].ICache) = \ > + }, = \ > + = \ > + /* L1 data cache parameters */ = \ > + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ > + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ > + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ > + Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ > + /* Next level of cache */ = \ > + SIZE_64KB, /* Size */ = \ > + 256, /* Num of sets */ = \ > + 4, /* Associativity */ = \ > + PPTT_DATA_CACHE_ATTR, /* Attributes */ = \ > + 64, /* Line size */ = \ > + RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1DataCache) = \ > + /* Cache id */ = \ > + ), = \ > + = \ > + /* L1 instruction cache parameters */ = \ > + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ > + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ > + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ > + Package.Cluster[ClusterId].Core[CpuId].L2Cache), = \ > + /* Next level of cache */ = \ > + SIZE_64KB, /* Size */ = \ > + 256, /* Num of sets */ = \ > + 4, /* Associativity */ = \ > + PPTT_INST_CACHE_ATTR, /* Attributes */ = \ > + 64, /* Line size */ = \ > + RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1InstructionCache) = \ > + /* Cache id */ = \ > + ), = \ > + = \ > + /* L2 cache parameters */ = \ > + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( = \ > + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ = \ > + 0, /* Next level of cache */ = \ > + SIZE_2MB, /* Size */ = \ > + 4096, /* Num of sets */ = \ > + 8, /* Associativity */ = \ > + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ = \ > + 64, /* Line size */ = \ > + RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L2Cache) = \ > + /* Cache id */ = \ > + ), = \ > + } > + > +/** Define helper macro for populating processor container information. > + > + @param [in] PackageId Package instance number. > + @param [in] ClusterId Cluster instance number. > +**/ > +#define PPTT_CLUSTER_INIT(PackageId, ClusterId) = \ > + { = \ > + /* Parameters for Cluster */ = \ > + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( = \ > + OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ = \ > + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ = \ > + OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, = \ > + Package), /* Parent */ = \ > + ((PackageId << 4) | ClusterId), /* ACPI Id */ = \ > + 0 /* Num of private resource *= / \ > + ), = \ > + = \ > + /* Initialize child core */ = \ > + { = \ > + PPTT_CORE_INIT (PackageId, ClusterId, 0) = \ > + } = \ > + } > + > +#pragma pack(1) > +/* > + * Processor Properties Topology Table > + */ > +typedef struct { > + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; > + RD_PPTT_PACKAGE Package; > +} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; > +#pragma pack () > + > +STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D { > + { > + ARM_ACPI_HEADER ( > + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU= RE, > + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, > + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION > + ) > + }, > + > + { > + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( > + OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]), > + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0), > + > + { > + PPTT_CLUSTER_INIT (0, 0), > + PPTT_CLUSTER_INIT (0, 1), > + PPTT_CLUSTER_INIT (0, 2), > + PPTT_CLUSTER_INIT (0, 3), > + PPTT_CLUSTER_INIT (0, 4), > + PPTT_CLUSTER_INIT (0, 5), > + PPTT_CLUSTER_INIT (0, 6), > + PPTT_CLUSTER_INIT (0, 7), > + PPTT_CLUSTER_INIT (0, 8), > + PPTT_CLUSTER_INIT (0, 9), > + PPTT_CLUSTER_INIT (0, 10), > + PPTT_CLUSTER_INIT (0, 11), > + PPTT_CLUSTER_INIT (0, 12), > + PPTT_CLUSTER_INIT (0, 13), > + PPTT_CLUSTER_INIT (0, 14), > + PPTT_CLUSTER_INIT (0, 15) > + } > + } > +}; > + > +/* > + * Reference the table being generated to prevent the optimizer from rem= oving > + * the data structure from the executable > + */ > +VOID* CONST ReferenceAcpiTable =3D &Pptt; -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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