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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C X-Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EDD5.mail.protection.outlook.com (10.167.241.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7202.16 via Frontend Transport; Wed, 17 Jan 2024 09:55:52 +0000 X-Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Wed, 17 Jan 2024 03:55:51 -0600 X-Received: from BLR-LAB-SFW01.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.34 via Frontend Transport; Wed, 17 Jan 2024 03:55:50 -0600 From: "Abdul Lateef Attar via groups.io" To: CC: Abdul Lateef Attar , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [edk2-devel] [PATCH v2 2/2] UefiCpuPkg/BaseXApic[X2]ApicLib: Implements AMD extended cpu topology Date: Wed, 17 Jan 2024 15:25:38 +0530 Message-ID: <64839533d33fb34b1568d78d26c5e7900c40cad5.1705484942.git.AbdulLateef.Attar@amd.com> In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD5:EE_|BN9PR12MB5260:EE_ X-MS-Office365-Filtering-Correlation-Id: e1905b79-fed3-4e37-7c5b-08dc17427dda X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: zviswxy6BOla80AnfGxvwlGNeDzSX2lZ47PV9nBodpoiR8n34kCZdqY7bm31pRtJq6EkDfe3YiKzGEL4BT3yiC91j6bSMBq9IGsDDeRk38dd79QBaCEIgODVzLXPKPxUqkxyIQ3CE0ev/0hQqJizRrDYHSRtg3MXpJe08tRuI/6DmhE8jW4YmtVMofI+xrV3MD4AlRwN8Ni02XMU9DK3Ctax3pCqqNM7K/4XWm6kPrUzFEz1X+yPIpyVAyQCA3PxJiA/QXAZTqfPvRoxJsIGfTP/is4445m9OtTLxpry1F1gPzUtRPnr4Ld4HgIDVIDSCLILNKPtSWDVWuAtjhHRyanmlpmxX9a7wcZX24O2H1RpwpndHRaDDX3MuJ7OO+2bB4jvqSJ3yRzyP/UfMBDgRTWsWyZtBr7MZLNFcF29uAqQNkQDdohNWKEOSm+JaE+CdrnHp4JebQc2MQGhC0HkilFz44lYv13bOyhEPTTyUUlukN2NfdXJEcBiqWTv2DAAbbM2qROa1xVE480Uw1lZJSRxozROGIdkbu7uF8ySM+yEnnm3pP5SJU+Jxbu7AYlrsXvkR2OMffUXGJgj3PHQKwDQFsMO2ct0UldW3kRBIRjDuRBlNIrNKXOfMw3drLUd3n/nrgWcJKtfy6j1HGGp7Gh4UdU8dFW+o0EthqWEodH2WPgMBFvxAs6MwIVuL0TBcmV5fFNw1pNrmpe8O/dw04qhVJsLT7mrjP3TR7S3uRfXGAocZepppzm7PMMBPpg9qHYRrZOvgH26fnYsl1mJvg== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jan 2024 09:55:52.5425 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e1905b79-fed3-4e37-7c5b-08dc17427dda X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5260 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,AbdulLateef.Attar@amd.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: KSAC7BdY7lxNueDQ3MNQ7enQx7686176AA= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b="j+JKte/j"; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}"); dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io From: Abdul Lateef Attar This patch adds support for AMD's new extended topology. If processor supports CPUID 80000026 leaf then obtain the topology information using new method. Algorithm: if CPUID is AMD: then check for AMD's extended cpu tology leaf. if yes then extract cpu tology based on AMD programmer manual's instruction. else then fallback to existing topology function. endif endif Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Signed-off-by: Abdul Lateef Attar --- .../Library/BaseXApicLib/BaseXApicLib.c | 126 +++++++++++++++++- .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 126 +++++++++++++++++- 2 files changed, 250 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Li= brary/BaseXApicLib/BaseXApicLib.c index efb9d71ca1..c4457d98b3 100644 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c @@ -4,7 +4,7 @@ This local APIC library instance supports xAPIC mode only. =20 Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.
- Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.
+ Copyright (c) 2017 - 2024, AMD Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -1157,6 +1157,125 @@ GetProcessorLocationByApicId ( } } =20 +/** + Get Package ID/Die ID/Module ID/Core ID/Thread ID of a AMD processor fam= ily. + + The algorithm assumes the target system has symmetry across physical + package boundaries with respect to the number of threads per core, numbe= r of + cores per module, number of modules per die, number + of dies per package. + + @param[in] InitialApicId Initial APIC ID of the target logical process= or. + @param[out] Package Returns the processor package ID. + @param[out] Die Returns the processor die ID. + @param[out] Tile Returns zero. + @param[out] Module Returns the processor module ID. + @param[out] Core Returns the processor core ID. + @param[out] Thread Returns the processor thread ID. +**/ +VOID +AmdGetProcessorLocation2ByApicId ( + IN UINT32 InitialApicId, + OUT UINT32 *Package OPTIONAL, + OUT UINT32 *Die OPTIONAL, + OUT UINT32 *Tile OPTIONAL, + OUT UINT32 *Module OPTIONAL, + OUT UINT32 *Core OPTIONAL, + OUT UINT32 *Thread OPTIONAL + ) +{ + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + UINT32 MaxExtendedCpuIdIndex; + UINT32 TopologyLevel; + UINT32 PreviousLevel; + UINT32 Data; + + if (Die !=3D NULL) { + *Die =3D 0; + } + + if (Tile !=3D NULL) { + *Tile =3D 0; + } + + if (Module !=3D NULL) { + *Module =3D 0; + } + + PreviousLevel =3D 0; + TopologyLevel =3D 0; + + /// Check if extended toplogy supported + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, N= ULL); + if (MaxExtendedCpuIdIndex >=3D AMD_CPUID_EXTENDED_TOPOLOGY) { + do { + AsmCpuidEx ( + AMD_CPUID_EXTENDED_TOPOLOGY, + TopologyLevel, + &ExtendedTopologyEax.Uint32, + &ExtendedTopologyEbx.Uint32, + &ExtendedTopologyEcx.Uint32, + NULL + ); + + if (ExtendedTopologyEbx.Bits.LogicalProcessors =3D=3D CPUID_EXTENDED= _TOPOLOGY_LEVEL_TYPE_INVALID) { + /// if this fails at first level + /// then will fall back to non-extended topology + break; + } + + Data =3D InitialApicId >> PreviousLevel; + Data &=3D (1 << (ExtendedTopologyEax.Bits.ApicIdShift - PreviousLeve= l)) - 1; + + switch (ExtendedTopologyEcx.Bits.LevelType) { + case CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT: + if (Thread !=3D NULL) { + *Thread =3D Data; + } + + break; + case CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE: + if (Core !=3D NULL) { + *Core =3D Data; + } + + break; + case CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE: + if (Module !=3D NULL) { + *Module =3D Data; + } + + break; + case CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE: + if (Die !=3D NULL) { + *Die =3D Data; + } + + break; + default: + break; + } + + TopologyLevel++; + PreviousLevel =3D ExtendedTopologyEax.Bits.ApicIdShift; + } while (ExtendedTopologyEbx.Bits.LogicalProcessors !=3D CPUID_EXTENDE= D_TOPOLOGY_LEVEL_TYPE_INVALID); + + if (Package !=3D NULL) { + *Package =3D InitialApicId >> PreviousLevel; + } + } + + /// If extended topology CPUID is not supported + /// OR, execution of AMD_CPUID_EXTENDED_TOPOLOGY at level 0 fails(return= 0). + if (TopologyLevel =3D=3D 0) { + GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread); + } + + return; +} + /** Get Package ID/Die ID/Tile ID/Module ID/Core ID/Thread ID of a processor= . =20 @@ -1194,6 +1313,11 @@ GetProcessorLocation2ByApicId ( UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_= DIE + 2]; UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_= TYPE_DIE + 2]; =20 + if (StandardSignatureIsAuthenticAMD ()) { + AmdGetProcessorLocation2ByApicId (InitialApicId, Package, Die, Tile, M= odule, Core, Thread); + return; + } + for (LevelType =3D 0; LevelType < ARRAY_SIZE (Bits); LevelType++) { Bits[LevelType] =3D 0; } diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/U= efiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index c0a8475833..0560d38ce5 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -5,7 +5,7 @@ which have xAPIC and x2APIC modes. =20 Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.
- Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.
+ Copyright (c) 2017 - 2024, AMD Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -1396,6 +1396,125 @@ GetProcessorLocationByApicId ( } } =20 +/** + Get Package ID/Die ID/Module ID/Core ID/Thread ID of a AMD processor fam= ily. + + The algorithm assumes the target system has symmetry across physical + package boundaries with respect to the number of threads per core, numbe= r of + cores per module, number of modules per die, number + of dies per package. + + @param[in] InitialApicId Initial APIC ID of the target logical process= or. + @param[out] Package Returns the processor package ID. + @param[out] Die Returns the processor die ID. + @param[out] Tile Returns zero. + @param[out] Module Returns the processor module ID. + @param[out] Core Returns the processor core ID. + @param[out] Thread Returns the processor thread ID. +**/ +VOID +AmdGetProcessorLocation2ByApicId ( + IN UINT32 InitialApicId, + OUT UINT32 *Package OPTIONAL, + OUT UINT32 *Die OPTIONAL, + OUT UINT32 *Tile OPTIONAL, + OUT UINT32 *Module OPTIONAL, + OUT UINT32 *Core OPTIONAL, + OUT UINT32 *Thread OPTIONAL + ) +{ + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + UINT32 MaxExtendedCpuIdIndex; + UINT32 TopologyLevel; + UINT32 PreviousLevel; + UINT32 Data; + + if (Die !=3D NULL) { + *Die =3D 0; + } + + if (Tile !=3D NULL) { + *Tile =3D 0; + } + + if (Module !=3D NULL) { + *Module =3D 0; + } + + PreviousLevel =3D 0; + TopologyLevel =3D 0; + + /// Check if extended toplogy supported + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, N= ULL); + if (MaxExtendedCpuIdIndex >=3D AMD_CPUID_EXTENDED_TOPOLOGY) { + do { + AsmCpuidEx ( + AMD_CPUID_EXTENDED_TOPOLOGY, + TopologyLevel, + &ExtendedTopologyEax.Uint32, + &ExtendedTopologyEbx.Uint32, + &ExtendedTopologyEcx.Uint32, + NULL + ); + + if (ExtendedTopologyEbx.Bits.LogicalProcessors =3D=3D CPUID_EXTENDED= _TOPOLOGY_LEVEL_TYPE_INVALID) { + /// if this fails at first level + /// then will fall back to non-extended topology + break; + } + + Data =3D InitialApicId >> PreviousLevel; + Data &=3D (1 << (ExtendedTopologyEax.Bits.ApicIdShift - PreviousLeve= l)) - 1; + + switch (ExtendedTopologyEcx.Bits.LevelType) { + case CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT: + if (Thread !=3D NULL) { + *Thread =3D Data; + } + + break; + case CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE: + if (Core !=3D NULL) { + *Core =3D Data; + } + + break; + case CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE: + if (Module !=3D NULL) { + *Module =3D Data; + } + + break; + case CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE: + if (Die !=3D NULL) { + *Die =3D Data; + } + + break; + default: + break; + } + + TopologyLevel++; + PreviousLevel =3D ExtendedTopologyEax.Bits.ApicIdShift; + } while (ExtendedTopologyEbx.Bits.LogicalProcessors !=3D CPUID_EXTENDE= D_TOPOLOGY_LEVEL_TYPE_INVALID); + + if (Package !=3D NULL) { + *Package =3D InitialApicId >> PreviousLevel; + } + } + + /// If extended topology CPUID is not supported + /// OR, execution of AMD_CPUID_EXTENDED_TOPOLOGY at level 0 fails(return= 0). + if (TopologyLevel =3D=3D 0) { + GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread); + } + + return; +} + /** Get Package ID/Die ID/Tile ID/Module ID/Core ID/Thread ID of a processor= . =20 @@ -1433,6 +1552,11 @@ GetProcessorLocation2ByApicId ( UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_= DIE + 2]; UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_= TYPE_DIE + 2]; =20 + if (StandardSignatureIsAuthenticAMD ()) { + AmdGetProcessorLocation2ByApicId (InitialApicId, Package, Die, Tile, M= odule, Core, Thread); + return; + } + for (LevelType =3D 0; LevelType < ARRAY_SIZE (Bits); LevelType++) { Bits[LevelType] =3D 0; } --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113943): https://edk2.groups.io/g/devel/message/113943 Mute This Topic: https://groups.io/mt/103782768/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-