From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=ryszard.knop@linux.intel.com; receiver=edk2-devel@lists.01.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E18B82194D3AE for ; Tue, 29 Jan 2019 05:54:34 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Jan 2019 05:54:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,537,1539673200"; d="scan'208";a="314515450" Received: from linux.intel.com ([10.54.29.200]) by fmsmga006.fm.intel.com with ESMTP; 29 Jan 2019 05:54:33 -0800 Received: from torii (torii.igk.intel.com [10.102.24.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by linux.intel.com (Postfix) with ESMTPS id DA284580550; Tue, 29 Jan 2019 05:54:31 -0800 (PST) Message-ID: <66c4b88177eec78e3a52d854e7f1281508922c0b.camel@linux.intel.com> From: Ryszard Knop To: Ard Biesheuvel , edk2-devel@lists.01.org Cc: kamil.kacperski@intel.com, eric.jin@intel.com, pawel.orlowski@intel.com, michael.d.kinney@intel.com, harry.l.hsiung@intel.com Date: Tue, 29 Jan 2019 14:54:29 +0100 In-Reply-To: <20181106175833.26964-2-ard.biesheuvel@linaro.org> References: <20181106175833.26964-1-ard.biesheuvel@linaro.org> <20181106175833.26964-2-ard.biesheuvel@linaro.org> Organization: Intel Corporation User-Agent: Evolution 3.30.4 Mime-Version: 1.0 Subject: Re: [PATCH edk2-staging 01/19] IntelOpenSourceUndiPkg.dsc: add AARCH64 and ARM to supported architectures X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 X-List-Received-Date: Tue, 29 Jan 2019 13:54:35 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit One thing of note here: We're primarily using MSVC for IA32/X64 builds, and that's the only thing we "officially" support. I'll try to build and test GCC binaries once in a while as well, but things might break once now and then. Our team also doesn't have any ARM hardware to test this on, so I'd appreciate any reports if it breaks :) Reviewed-by: Ryszard Knop On Tue, 2018-11-06 at 18:58 +0100, ard.biesheuvela wrote: > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > IntelUndiPkg/IntelOpenSourceUndiPkg.dsc | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > > diff --git a/IntelUndiPkg/IntelOpenSourceUndiPkg.dsc > b/IntelUndiPkg/IntelOpenSourceUndiPkg.dsc > index 21b1fb27984e..ca440bde2cb4 100644 > --- a/IntelUndiPkg/IntelOpenSourceUndiPkg.dsc > +++ b/IntelUndiPkg/IntelOpenSourceUndiPkg.dsc > @@ -29,7 +29,7 @@ > PLATFORM_VERSION = 0.1 > DSC_SPECIFICATION = 0x00010005 > OUTPUT_DIRECTORY = Build/IntelUndiPkg > - SUPPORTED_ARCHITECTURES = IA32|IPF|X64 > + SUPPORTED_ARCHITECTURES = IA32|IPF|X64|ARM|AARCH64 > BUILD_TARGETS = DEBUG|RELEASE|DEV > SKUID_IDENTIFIER = DEFAULT > > @@ -62,6 +62,17 @@ > SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynch > ronizationLib.inf > DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib > /BaseDebugPrintErrorLevelLib.inf > > +[LibraryClasses.ARM, LibraryClasses.AARCH64] > + # > + # It is not possible to prevent the ARM compiler from inserting > calls to > + # intrinsic functions. This library provides the instrinsic > functions such > + # a compiler may generate calls to. > + # > + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.in > f > + > + # Add support for GCC stack protector > + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf > + > #################################################################### > ############ > # > # Pcd Section - list of all EDK II PCD Entries defined by this > Platform