From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 46E98AC15B6 for ; Fri, 2 Feb 2024 14:38:49 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=hBblOUtvQMb9Bk1Th80XITBclbz1GIkjFCn+oLVLiyw=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1706884727; v=1; b=pNhcOf9oCzpE9DhIGUroIlVTYmROqudMBFFgAsxIRKRE8IA2osaTnFPg7ZgFqZgfJS9l8g25 QKbiPyQtgzSlVfBMxv/ojk4dBRRqY0X1ijM1CpTO7RrCkqYXNDRfiaGtk7i378MwJig/JZII1v2 ZWe0MJ6CzkVYyaw/njkAMF7w= X-Received: by 127.0.0.2 with SMTP id Tz6cYY7687511xezbAFseRyy; Fri, 02 Feb 2024 06:38:47 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by mx.groups.io with SMTP id smtpd.web10.17650.1706855555979552209 for ; Thu, 01 Feb 2024 22:32:36 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10971"; a="3938631" X-IronPort-AV: E=Sophos;i="6.05,237,1701158400"; d="scan'208";a="3938631" X-Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Feb 2024 22:32:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,237,1701158400"; d="scan'208";a="30820355" X-Received: from chsuehx-desk.gar.corp.intel.com ([10.225.77.6]) by orviesa002.jf.intel.com with ESMTP; 01 Feb 2024 22:32:32 -0800 From: dorax.hsueh@intel.com To: devel@edk2.groups.io Cc: DoraX Hsueh , Sai Chaganty , Rosen Chuang , Saloni Kasbekar , Haoyu Tang Subject: [edk2-devel] [PATCH] AlderlakeSiliconPkg: Update for SPI2 Protocol and Identify flash regions by GUID Date: Fri, 2 Feb 2024 14:32:26 +0800 Message-Id: <68bd889bdb0b6ce4f2bad700403d07e21f73aa74.1706855436.git.dorax.hsueh@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dorax.hsueh@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 5yUp8AE8H8P8oLfun5OYKZnlx7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=pNhcOf9o; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io From: DoraX Hsueh https://bugzilla.tianocore.org/show_bug.cgi?id=3D4664 1. Updates references to the "PCH_SPI_PROTOCOL" to instead refer to "PCH_SP= I2_PROTOCOL". 2. Updates the library to identify flash regions by GUID and internally map the GUID entries to values specific to AlderlakeSiliconPkg. 3. Libs/modules that need to reference IntelSiliconPkg are updated. 4. Add gUsbConfigGuid to fix USB not working issue in OS. Cc: Sai Chaganty Cc: Rosen Chuang Cc: Saloni Kasbekar Cc: Haoyu Tang Signed-off-by: DoraX Hsueh --- .../Cpu/Include/Register/CommonMsr.h | 4 + .../Fru/AdlPch/CommonLib.dsc | 2 +- .../AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc | 2 - .../Include/ConfigBlock/Usb/UsbConfig.h | 223 ++++++++ .../Include/Library/SpiAccessLib.h | 44 ++ .../Include/Register/PttPtpRegs.h | 27 + .../Spi/IncludePrivate/Library/SpiCommonLib.h | 60 +-- .../Spi/IncludePrivate/Register/SpiRegs.h | 9 +- .../PeiDxeSmmSpiAccessLib.inf | 33 ++ .../PeiDxeSmmSpiAccessLib/SpiAccessLib.c | 75 +++ .../IpBlock/Spi/Library/PeiSpiLib/PchSpi.c | 2 +- .../Spi/Library/PeiSpiLib/PeiSpiLib.inf | 2 +- .../BaseSpiCommonLib/BaseSpiCommonLib.inf | 19 +- .../BaseSpiCommonLib/SpiCommon.c | 494 ++++++++++++------ .../AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c | 34 +- .../IpBlock/Spi/Smm/SpiSmm.inf | 5 +- .../IncludePrivate/Library/SmmPchPrivateLib.h | 27 + .../SmmPchPrivateLib/SmmPchPrivateLib.c | 83 +++ .../SmmPchPrivateLib/SmmPchPrivateLib.inf | 32 ++ .../Product/Alderlake/SiPkgDxeLib.dsc | 5 + Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec | 7 +- 21 files changed, 990 insertions(+), 199 deletions(-) create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/U= sb/UsbConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiAc= cessLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PttP= tpRegs.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/P= eiDxeSmmSpiAccessLib/PeiDxeSmmSpiAccessLib.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/P= eiDxeSmmSpiAccessLib/SpiAccessLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/IncludePrivate/Li= brary/SmmPchPrivateLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/LibraryPrivate/Sm= mPchPrivateLib/SmmPchPrivateLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/LibraryPrivate/Sm= mPchPrivateLib/SmmPchPrivateLib.inf diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/Register/CommonM= sr.h b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h index caa0e67b..44a476c0 100644 --- a/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h +++ b/Silicon/Intel/AlderlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h @@ -56,5 +56,9 @@ typedef union { =0D } MSR_CORE_THREAD_COUNT_REGISTER;=0D =0D +/**=0D + Special Chipset Usage MSR=0D +**/=0D +#define MSR_SPCL_CHIPSET_USAGE 0x000001FE=0D =0D #endif /* _COMMONMSR_h */=0D diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc b/S= ilicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc index 3f508f83..ee5800a9 100644 --- a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc @@ -11,7 +11,7 @@ =0D EspiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Espi/Library/PeiDxeSmmEspiLib/Pei= DxeSmmEspiLib.inf=0D =0D -=0D + SpiAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Library/PeiDxeSmmSpiAcce= ssLib/PeiDxeSmmSpiAccessLib.inf=0D PmcLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxe= SmmPmcLib.inf=0D PmcPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/LibraryPrivate/PeiDxeSm= mPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf=0D SpiCommonLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/LibraryPrivate/BaseSpiCo= mmonLib/BaseSpiCommonLib.inf=0D diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc b/Sili= con/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc index ebe2bbfd..cbaf8e37 100644 --- a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc @@ -5,8 +5,6 @@ # SPDX-License-Identifier: BSD-2-Clause-Patent=0D ##=0D =0D - SpiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.in= f=0D -=0D GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiGpi= oHelpersLib/PeiGpioHelpersLib.inf=0D =0D =0D diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Usb/UsbC= onfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Usb/UsbConf= ig.h new file mode 100644 index 00000000..47bc86cd --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Usb/UsbConfig.h @@ -0,0 +1,223 @@ +/** @file=0D + Common USB policy shared between PCH and CPU=0D + Contains general features settings for xHCI and xDCI=0D +=0D +@copyright=0D + INTEL CONFIDENTIAL=0D + Copyright 2017 - 2021 Intel Corporation.=0D +=0D + The source code contained or described herein and all documents related = to the=0D + source code ("Material") are owned by Intel Corporation or its suppliers= or=0D + licensors. Title to the Material remains with Intel Corporation or its s= uppliers=0D + and licensors. The Material may contain trade secrets and proprietary an= d=0D + confidential information of Intel Corporation and its suppliers and lice= nsors,=0D + and is protected by worldwide copyright and trade secret laws and treaty= =0D + provisions. No part of the Material may be used, copied, reproduced, mod= ified,=0D + published, uploaded, posted, transmitted, distributed, or disclosed in a= ny way=0D + without Intel's prior express written permission.=0D +=0D + No license under any patent, copyright, trade secret or other intellectu= al=0D + property right is granted to or conferred upon you by disclosure or deli= very=0D + of the Materials, either expressly, by implication, inducement, estoppel= or=0D + otherwise. Any license under such intellectual property rights must be=0D + express and approved by Intel in writing.=0D +=0D + Unless otherwise agreed by Intel in writing, you may not remove or alter= =0D + this notice or any other notice embedded in Materials by Intel or=0D + Intel's suppliers or licensors in any way.=0D +=0D + This file contains an 'Intel Peripheral Driver' and is uniquely identifi= ed as=0D + "Intel Reference Module" and is licensed for Intel CPUs and chipsets und= er=0D + the terms of your license agreement with Intel or your vendor. This file= may=0D + be modified by the user, subject to additional terms of the license agre= ement.=0D +=0D +@par Specification Reference:=0D +**/=0D +#ifndef _USB_CONFIG_H_=0D +#define _USB_CONFIG_H_=0D +=0D +#define USB_CONFIG_REVISION 3=0D +extern EFI_GUID gUsbConfigGuid;=0D +=0D +#define MAX_USB2_PORTS 16=0D +#define MAX_USB3_PORTS 10=0D +=0D +#pragma pack (push,1)=0D +=0D +typedef UINT8 USB_OVERCURRENT_PIN;=0D +#define USB_OC_SKIP 0xFF=0D +#define USB_OC_MAX_PINS 16 ///< Total OC pins number (both p= hysical and virtual)=0D +=0D +/**=0D + This structure configures per USB2.0 port settings like enabling and ove= rcurrent protection=0D +**/=0D +typedef struct {=0D + /**=0D + These members describe the specific over current pin number of USB 2.0= Port N.=0D + It is SW's responsibility to ensure that a given port's bit map is set= only for=0D + one OC pin Description. USB2 and USB3 on the same combo Port must use = the same OC pin.=0D + **/=0D + UINT32 OverCurrentPin : 8;=0D + UINT32 Enable : 1; ///< 0: Disable; 1: Enab= le.=0D + UINT32 PortResetMessageEnable : 1; ///< 0: Disable USB2 Port R= eset Message; 1: Enable USB2 Port Reset Message=0D + UINT32 RsvdBits0 : 22; ///< Reserved bits=0D +} USB2_PORT_CONFIG;=0D +=0D +/**=0D + This structure configures per USB3.x port settings like enabling and ove= rcurrent protection=0D +**/=0D +typedef struct {=0D + /**=0D + These members describe the specific over current pin number of USB 3.x= Port N.=0D + It is SW's responsibility to ensure that a given port's bit map is set= only for=0D + one OC pin Description. USB2 and USB3 on the same combo Port must use = the same OC pin.=0D + **/=0D + UINT32 OverCurrentPin : 8;=0D + UINT32 Enable : 1; ///< 0: Disable; 1: Enable= .=0D + UINT32 RsvdBits0 : 23; ///< Reserved bits=0D +} USB3_PORT_CONFIG;=0D +=0D +/**=0D + The XDCI_CONFIG block describes the configurations=0D + of the xDCI Usb Device controller.=0D +**/=0D +typedef struct {=0D + /**=0D + This member describes whether or not the xDCI controller should be ena= bled.=0D + 0: Disable; 1: Enable.=0D + **/=0D + UINT32 Enable : 1;=0D + UINT32 RsvdBits0 : 31; ///< Reserved bits=0D +} XDCI_CONFIG;=0D +=0D +//=0D +// PCH:RestrictedBegin=0D +//=0D +//=0D +// USB EP Type Lock Policy=0D +//=0D +typedef struct {=0D + UINT32 TestEPTypeLockPolicy;=0D + UINT32 TestEPTypeLockPolicyPortControl1; // NO USE=0D + UINT32 TestEPTypeLockPolicyPortControl2; // NO USE=0D +} PCH_USB30_EP_TYPE_LOCK_POLICY_SETTINGS;=0D +//=0D +// PCH:RestrictedEnd=0D +//=0D +=0D +/**=0D + This member describes the expected configuration of the USB controller,= =0D + Platform modules may need to refer Setup options, schematic, BIOS specif= ication to update this field.=0D + The Usb20OverCurrentPins and Usb30OverCurrentPins field must be updated = by referring the schematic.=0D +=0D + Revision 1:=0D + - Initial version.=0D + Revision 2:=0D + - Added UaolEnable to control USB Audio Offload Capability.=0D + Revision 3:=0D + - Add HsiiEnable enable option to control HSII feature=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er=0D + /**=0D + This policy option when set will make BIOS program Port Disable Overri= de register during PEI phase.=0D + When disabled BIOS will not program the PDO during PEI phase and leave= PDO register unlocked for later programming.=0D + If this is disabled, platform code MUST set it before booting into OS.= =0D + 1: Enable=0D + 0: Disable=0D + **/=0D + UINT32 PdoProgramming : 1;=0D + /**=0D + This option allows for control whether USB should program the Overcurr= ent Pins mapping into xHCI.=0D + Disabling this feature will disable overcurrent detection functionalit= y.=0D + Overcurrent Pin mapping data is contained in respective port structure= s (i.e. USB30_PORT_CONFIG) in OverCurrentPin field.=0D + By default this Overcurrent functionality should be enabled and disabl= ed only for OBS debug usage.=0D + 1: Will program USB OC pin mapping in respective xHCI controller re= gisters=0D + 0: Will clear OC pin mapping allow for OBS usage of OC pins=0D + **/=0D + UINT32 OverCurrentEnable : 1;=0D + /**=0D + (Test)=0D + If this policy option is enabled then BIOS will program OCCFDONE bit i= n xHCI meaning that OC mapping data will be=0D + consumed by xHCI and OC mapping registers will be locked. OverCurrent = mapping data is taken from respective port data=0D + structure from OverCurrentPin field.=0D + If EnableOverCurrent policy is enabled this also should be enabled, ot= herwise xHCI won't consume OC mapping data.=0D + 1: Program OCCFDONE bit and make xHCI consume OverCurrent mapping d= ata=0D + 0: Do not program OCCFDONE bit making it possible to use OBS debug on = OC pins.=0D + **/=0D + UINT32 XhciOcLock : 1;=0D + /**=0D + Enabling this feature will allow for overriding LTR values for xHCI co= ntroller.=0D + Values used for programming will be taken from this config block and B= IOS will disregard recommended ones.=0D + 0: disable - do not override recommended LTR values=0D + 1: enable - override recommended LTR values=0D + **/=0D + UINT32 LtrOverrideEnable : 1;=0D + /**=0D + Enable/disable option for USB Audio Offload feture. Disabling this wil= l disable UAOL capability=0D + in xHCI and UAOL ACPI definitions will be hidden.=0D + 0: disable UAOL=0D + 1: enable UAOL=0D + **/=0D + UINT32 UaolEnable : 1;=0D + /**=0D + Enable HS Interrupt IN Alarm=0D + 0: disable - Disable HSII=0D + 1: enable - Enable HSII=0D + **/=0D + UINT32 HsiiEnable : 1;=0D + UINT32 RsvdBits0 : 26; ///< Rese= rved bits=0D + /**=0D + High Idle Time Control override value=0D + This setting is used only if LtrOverrideEnable is enabled=0D + **/=0D + UINT32 LtrHighIdleTimeOverride;=0D + /**=0D + Medium Idle Time Control override value=0D + This setting is used only if LtrOverrideEnable is enabled=0D + **/=0D + UINT32 LtrMediumIdleTimeOverride;=0D + /**=0D + Low Idle Time Control override value=0D + This setting is used only if LtrOverrideEnable is enabled=0D + **/=0D + UINT32 LtrLowIdleTimeOverride;=0D + /**=0D + These members describe whether the USB2 Port N of PCH is enabled by pl= atform modules.=0D + **/=0D + USB2_PORT_CONFIG PortUsb20[MAX_USB2_PORTS];=0D + /**=0D + These members describe whether the USB3 Port N of PCH is enabled by pl= atform modules.=0D + **/=0D + USB3_PORT_CONFIG PortUsb30[MAX_USB3_PORTS];=0D + /**=0D + This member describes whether or not the xDCI controller should be ena= bled.=0D + **/=0D + XDCI_CONFIG XdciConfig;=0D +=0D +//=0D +// PCH:RestrictedBegin=0D +//=0D + PCH_USB30_EP_TYPE_LOCK_POLICY_SETTINGS Usb30EpTypeLockPolicySettings;=0D + UINT32 XhciSafeMode : 1;=0D + UINT32 XdciSafeMode : 1;=0D + UINT32 TestControllerEnabled : 1; ///< 0: Disable; 1: Enable. R= emark: Can be disabled only for debugging process!!!=0D + UINT32 TestUnlockUsbForSvNoa : 1; ///< 1: Unlock to enable NOA = usage. 0: Set Xhci OC registers, Set Xhci OCCDone bit, XHCI Access Control= Bit. Policy for SV usage. NO USE.=0D + UINT32 TestClkGatingXhci : 1; ///< 1: Enable XHCI Clock Gat= ing. 0: Disable XHCI Clock Gating. Policy for SV usage. NO USE.=0D + /**=0D + Ater xHCI is initialized, BIOS should lock the xHCI configuration regist= ers to RO.=0D + This prevents any unintended changes. BIOS should set these bits to lock= down the settings prior to end of POST=0D + 0: POR is XHCI Access Control Bit is set and locks the registers;=0D + 1: Enable XHCI Access Control Bit is set and locks the registers;=0D + 2: Clear/Disable XHCI Access Control Bit is cleared and the registers ar= e unlocked.=0D + **/=0D + UINT32 TestXhciAccessControlLock : 2;=0D + UINT32 RsvdBits1 : 25; ///< Reserved bits=0D +//=0D +// PCH:RestrictedEnd=0D +//=0D +} USB_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _USB_CONFIG_H_=0D diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiAccessLib= .h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiAccessLib.h new file mode 100644 index 00000000..6e7f48fe --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiAccessLib.h @@ -0,0 +1,44 @@ +/** @file=0D + SPI library header for abstraction of SPI HW registers accesses=0D +=0D + Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +#ifndef _SPI_ACCESS_LIB_H_=0D +#define _SPI_ACCESS_LIB_H_=0D +=0D +=0D +/**=0D + Returns SPI BAR0 value=0D +=0D + @retval UINT32 PCH SPI BAR0 value=0D +**/=0D +UINT32=0D +SpiGetBar0 (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks if PCH SPI Controler is present and available=0D +=0D + @retval TRUE PCH SPI controller is avaialable=0D + @retval FALSE PCH SPI controller is not available=0D +**/=0D +BOOLEAN=0D +SpiIsControllerAvailable (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks if Device Attached Flash (DAF) mode is active=0D +=0D + @retval TRUE SAF mode is active=0D + @retval FALSE SAF mode is not active=0D +**/=0D +BOOLEAN=0D +SpiIsSafModeActive (=0D + VOID=0D + );=0D +=0D +#endif // _SPI_ACCESS_LIB_H_=0D diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PttPtpRegs.= h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PttPtpRegs.h new file mode 100644 index 00000000..64569ed8 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PttPtpRegs.h @@ -0,0 +1,27 @@ +/** @file=0D + Register definitions for PTT HCI (Platform Trust Technology - Host Contr= oller Interface).=0D +=0D + Conventions:=0D +=0D + - Prefixes:=0D + Definitions beginning with "R_" are registers=0D + Definitions beginning with "B_" are bits within registers=0D + Definitions beginning with "V_" are meaningful values of bits within t= he registers=0D + Definitions beginning with "S_" are register sizes=0D + Definitions beginning with "N_" are the bit position=0D +=0D + Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +#ifndef _PTT_HCI_REGS_H_=0D +#define _PTT_HCI_REGS_H_=0D +=0D +///=0D +/// LT public space registers=0D +///=0D +#define R_LT_UCS 0xFED30880=0D +#define R_LT_EXISTS 0xFED30010=0D +=0D +=0D +#endif=0D diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/L= ibrary/SpiCommonLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Inclu= dePrivate/Library/SpiCommonLib.h index e13718c9..dc663198 100644 --- a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/= SpiCommonLib.h +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/= SpiCommonLib.h @@ -7,7 +7,7 @@ #ifndef _SPI_COMMON_LIB_H_=0D #define _SPI_COMMON_LIB_H_=0D =0D -#include =0D +#include =0D =0D //=0D // Maximum time allowed while waiting the SPI cycle to complete=0D @@ -49,7 +49,7 @@ typedef enum { typedef struct {=0D UINT32 Signature;=0D EFI_HANDLE Handle;=0D - PCH_SPI_PROTOCOL SpiProtocol;=0D + PCH_SPI2_PROTOCOL SpiProtocol;=0D UINT16 PchAcpiBase;=0D UINT64 PchSpiBase;=0D UINT8 ReadPermission;=0D @@ -157,8 +157,8 @@ IsSpiControllerSaveRestoreEnabled ( /**=0D Read data from the flash part.=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D - @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor.=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D + @param[in] FlashRegionGuid The Flash Region GUID for flash cycle wh= ich corresponds to the type in the descriptor.=0D @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions.=0D @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle.=0D @param[out] Buffer The Pointer to caller-allocated buffer c= ontaining the dada received.=0D @@ -171,8 +171,8 @@ IsSpiControllerSaveRestoreEnabled ( EFI_STATUS=0D EFIAPI=0D SpiProtocolFlashRead (=0D - IN PCH_SPI_PROTOCOL *This,=0D - IN FLASH_REGION_TYPE FlashRegionType,=0D + IN PCH_SPI2_PROTOCOL *This,=0D + IN EFI_GUID *FlashRegionGuid,=0D IN UINT32 Address,=0D IN UINT32 ByteCount,=0D OUT UINT8 *Buffer=0D @@ -181,8 +181,8 @@ SpiProtocolFlashRead ( /**=0D Write data to the flash part.=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D - @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor.=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D + @param[in] FlashRegionGuid The Flash Region GUID for flash cycle wh= ich corresponds to the type in the descriptor.=0D @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions.=0D @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle.=0D @param[in] Buffer Pointer to caller-allocated buffer conta= ining the data sent during the SPI cycle.=0D @@ -194,8 +194,8 @@ SpiProtocolFlashRead ( EFI_STATUS=0D EFIAPI=0D SpiProtocolFlashWrite (=0D - IN PCH_SPI_PROTOCOL *This,=0D - IN FLASH_REGION_TYPE FlashRegionType,=0D + IN PCH_SPI2_PROTOCOL *This,=0D + IN EFI_GUID *FlashRegionGuid,=0D IN UINT32 Address,=0D IN UINT32 ByteCount,=0D IN UINT8 *Buffer=0D @@ -204,8 +204,8 @@ SpiProtocolFlashWrite ( /**=0D Erase some area on the flash part.=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D - @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor.=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D + @param[in] FlashRegionGuid The Flash Region GUID for flash cycle wh= ich corresponds to the type in the descriptor.=0D @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions.=0D @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle.=0D =0D @@ -216,8 +216,8 @@ SpiProtocolFlashWrite ( EFI_STATUS=0D EFIAPI=0D SpiProtocolFlashErase (=0D - IN PCH_SPI_PROTOCOL *This,=0D - IN FLASH_REGION_TYPE FlashRegionType,=0D + IN PCH_SPI2_PROTOCOL *This,=0D + IN EFI_GUID *FlashRegionGuid,=0D IN UINT32 Address,=0D IN UINT32 ByteCount=0D );=0D @@ -225,7 +225,7 @@ SpiProtocolFlashErase ( /**=0D Read SFDP data from the flash part.=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D @param[in] ComponentNumber The Componen Number for chip select=0D @param[in] Address The starting byte address for SFDP data = read.=0D @param[in] ByteCount Number of bytes in SFDP data portion of = the SPI cycle=0D @@ -239,7 +239,7 @@ SpiProtocolFlashErase ( EFI_STATUS=0D EFIAPI=0D SpiProtocolFlashReadSfdp (=0D - IN PCH_SPI_PROTOCOL *This,=0D + IN PCH_SPI2_PROTOCOL *This,=0D IN UINT8 ComponentNumber,=0D IN UINT32 Address,=0D IN UINT32 ByteCount,=0D @@ -249,7 +249,7 @@ SpiProtocolFlashReadSfdp ( /**=0D Read Jedec Id from the flash part.=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D @param[in] ComponentNumber The Componen Number for chip select=0D @param[in] ByteCount Number of bytes in JedecId data portion = of the SPI cycle, the data size is 3 typically=0D @param[out] JedecId The Pointer to caller-allocated buffer c= ontaining JEDEC ID received=0D @@ -262,7 +262,7 @@ SpiProtocolFlashReadSfdp ( EFI_STATUS=0D EFIAPI=0D SpiProtocolFlashReadJedecId (=0D - IN PCH_SPI_PROTOCOL *This,=0D + IN PCH_SPI2_PROTOCOL *This,=0D IN UINT8 ComponentNumber,=0D IN UINT32 ByteCount,=0D OUT UINT8 *JedecId=0D @@ -271,7 +271,7 @@ SpiProtocolFlashReadJedecId ( /**=0D Write the status register in the flash part.=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically=0D @param[in] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register writing=0D =0D @@ -282,7 +282,7 @@ SpiProtocolFlashReadJedecId ( EFI_STATUS=0D EFIAPI=0D SpiProtocolFlashWriteStatus (=0D - IN PCH_SPI_PROTOCOL *This,=0D + IN PCH_SPI2_PROTOCOL *This,=0D IN UINT32 ByteCount,=0D IN UINT8 *StatusValue=0D );=0D @@ -290,7 +290,7 @@ SpiProtocolFlashWriteStatus ( /**=0D Read status register in the flash part.=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically=0D @param[out] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register received.=0D =0D @@ -301,7 +301,7 @@ SpiProtocolFlashWriteStatus ( EFI_STATUS=0D EFIAPI=0D SpiProtocolFlashReadStatus (=0D - IN PCH_SPI_PROTOCOL *This,=0D + IN PCH_SPI2_PROTOCOL *This,=0D IN UINT32 ByteCount,=0D OUT UINT8 *StatusValue=0D );=0D @@ -309,8 +309,8 @@ SpiProtocolFlashReadStatus ( /**=0D Get the SPI region base and size, based on the enum type=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D - @param[in] FlashRegionType The Flash Region type for for the base a= ddress which is listed in the Descriptor.=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D + @param[in] FlashRegionGuid The Flash Region GUID for flash cycle wh= ich corresponds to the type in the descriptor.=0D @param[out] BaseAddress The Flash Linear Address for the Region = 'n' Base=0D @param[out] RegionSize The size for the Region 'n'=0D =0D @@ -321,8 +321,8 @@ SpiProtocolFlashReadStatus ( EFI_STATUS=0D EFIAPI=0D SpiProtocolGetRegionAddress (=0D - IN PCH_SPI_PROTOCOL *This,=0D - IN FLASH_REGION_TYPE FlashRegionType,=0D + IN PCH_SPI2_PROTOCOL *This,=0D + IN EFI_GUID *FlashRegionGuid,=0D OUT UINT32 *BaseAddress,=0D OUT UINT32 *RegionSize=0D );=0D @@ -330,7 +330,7 @@ SpiProtocolGetRegionAddress ( /**=0D Read PCH Soft Strap Values=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA= .=0D @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle=0D @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining PCH Soft Strap Value.=0D @@ -344,7 +344,7 @@ SpiProtocolGetRegionAddress ( EFI_STATUS=0D EFIAPI=0D SpiProtocolReadPchSoftStrap (=0D - IN PCH_SPI_PROTOCOL *This,=0D + IN PCH_SPI2_PROTOCOL *This,=0D IN UINT32 SoftStrapAddr,=0D IN UINT32 ByteCount,=0D OUT VOID *SoftStrapValue=0D @@ -353,7 +353,7 @@ SpiProtocolReadPchSoftStrap ( /**=0D Read CPU Soft Strap Values=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUS= BA.=0D @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle.=0D @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining CPU Soft Strap Value.=0D @@ -367,7 +367,7 @@ SpiProtocolReadPchSoftStrap ( EFI_STATUS=0D EFIAPI=0D SpiProtocolReadCpuSoftStrap (=0D - IN PCH_SPI_PROTOCOL *This,=0D + IN PCH_SPI2_PROTOCOL *This,=0D IN UINT32 SoftStrapAddr,=0D IN UINT32 ByteCount,=0D OUT VOID *SoftStrapValue=0D diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/R= egister/SpiRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePr= ivate/Register/SpiRegs.h index 5cb47911..7e4414f8 100644 --- a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register= /SpiRegs.h +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register= /SpiRegs.h @@ -62,6 +62,8 @@ //=0D // BIOS Flash Program Registers (based on SPI_BAR0)=0D //=0D +#define R_SPI_MEM_BFPR 0x00 = ///< BIOS Flash Primary Region Register(32bits), which is RO and contains t= he same value from FREG1=0D +#define B_SPI_MEM_BFPR_SBRS BIT31 = ///< Shadowed BIOS Region Select=0D #define R_SPI_MEM_HSFSC 0x04 = ///< Hardware Sequencing Flash Status and Control Register(32bits)=0D #define B_SPI_MEM_HSFSC_FDBC_MASK 0x3F000000 = ///< Flash Data Byte Count ( <=3D 64), Count =3D (Value in this field) + 1.= =0D #define N_SPI_MEM_HSFSC_FDBC 24=0D @@ -78,12 +80,8 @@ #define B_SPI_MEM_HSFSC_CYCLE_FGO BIT16 = ///< Flash Cycle Go.=0D #define B_SPI_MEM_HSFSC_FDV BIT14 = ///< Flash Descriptor Valid, once valid software can use hareware sequencin= g regs=0D #define B_SPI_MEM_HSFSC_WRSDIS BIT11 = ///< Write Status Disable=0D -#define B_SPI_MEM_HSFSC_SAF_CE BIT8 = ///< SAF ctype error=0D -#define B_SPI_MEM_HSFSC_SAF_LE BIT6 = ///< SAF link error=0D +#define B_SPI_MEM_HSFSC_SAF_MODE_ACTIVE BIT7 = ///< Indicates flash is attached either directly to the PCH via the SPI bus= or EC/BMC=0D #define B_SPI_MEM_HSFSC_SCIP BIT5 = ///< SPI cycle in progress=0D -#define B_SPI_MEM_HSFSC_SAF_DLE BIT4 = ///< SAF Data length error=0D -#define B_SPI_MEM_HSFSC_SAF_ERROR BIT3 = ///< SAF Error=0D -#define B_SPI_MEM_HSFSC_AEL BIT2 = ///< Access Error Log=0D #define B_SPI_MEM_HSFSC_FCERR BIT1 = ///< Flash Cycle Error=0D #define B_SPI_MEM_HSFSC_FDONE BIT0 = ///< Flash Cycle Done=0D #define R_SPI_MEM_FADDR 0x08 = ///< SPI Flash Address=0D @@ -113,4 +111,5 @@ #define B_SPI_MEM_SFDPX_VSCCX_EO_64K BIT29 = ///< 64k Erase valid (EO_64k_valid)=0D #define R_SPI_MEM_SFDP1_VSCC1 0xC8 = ///< Vendor Specific Component Capabilities Register(32 bits)=0D =0D +=0D #endif=0D diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiDxeSm= mSpiAccessLib/PeiDxeSmmSpiAccessLib.inf b/Silicon/Intel/AlderlakeSiliconPkg= /IpBlock/Spi/Library/PeiDxeSmmSpiAccessLib/PeiDxeSmmSpiAccessLib.inf new file mode 100644 index 00000000..444c6b34 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiDxeSmmSpiAcc= essLib/PeiDxeSmmSpiAccessLib.inf @@ -0,0 +1,33 @@ +## @file=0D +# Component description file for PCH SPI access library=0D +#=0D +# Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D PeiDxeSmmSpiAccessLib=0D +FILE_GUID =3D A6D4C05A-F6CB-46D5-4BA1-8C47B139DCA6=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D SpiAccessLib=0D +=0D +=0D +[LibraryClasses]=0D +BaseLib=0D +IoLib=0D +DebugLib=0D +PciSegmentLib=0D +PchPciBdfLib=0D +PchPcrLib=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +AlderlakeSiliconPkg/SiPkg.dec=0D +=0D +=0D +[Sources]=0D +SpiAccessLib.c \ No newline at end of file diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiDxeSm= mSpiAccessLib/SpiAccessLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Sp= i/Library/PeiDxeSmmSpiAccessLib/SpiAccessLib.c new file mode 100644 index 00000000..da8475ea --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiDxeSmmSpiAcc= essLib/SpiAccessLib.c @@ -0,0 +1,75 @@ +/** @file=0D + SPI library for abstraction of SPI HW registers accesses=0D +=0D + Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +=0D +/**=0D + Checks if PCH SPI Controler is present and available=0D +=0D + @retval TRUE PCH SPI controller is avaialable=0D + @retval FALSE PCH SPI controller is not available=0D +**/=0D +BOOLEAN=0D +SpiIsControllerAvailable (=0D + VOID=0D + )=0D +{=0D + //=0D + // Checks for SPI controller=0D + //=0D + return (PciSegmentRead16 (SpiPciCfgBase () + PCI_VENDOR_ID_OFFSET) !=3D = 0xFFFF);=0D +}=0D +=0D +/**=0D + Returns PCH SPI BAR0 value=0D +=0D + @retval UINT32 PCH SPI BAR0 value=0D +**/=0D +UINT32=0D +SpiGetBar0 (=0D + VOID=0D + )=0D +{=0D + UINT32 SpiBar0;=0D +=0D + ASSERT (SpiIsControllerAvailable ());=0D + SpiBar0 =3D PciSegmentRead32 (SpiPciCfgBase () + R_SPI_CFG_BAR0) & ~B_SP= I_CFG_BAR0_MASK;=0D + ASSERT (SpiBar0 !=3D 0);=0D +=0D + return SpiBar0;=0D +}=0D +=0D +/**=0D + Checks if device Attached Flash (DAF) mode is active=0D +=0D + @retval TRUE SAF mode is active=0D + @retval FALSE SAF mode is not active=0D +**/=0D +BOOLEAN=0D +SpiIsSafModeActive (=0D + VOID=0D + )=0D +{=0D + UINT32 SpiBar0;=0D + SpiBar0 =3D SpiGetBar0 ();=0D +=0D + return !!(MmioRead32 (SpiBar0 + R_SPI_MEM_HSFSC) & B_SPI_MEM_HSFSC_SAF_M= ODE_ACTIVE);=0D +} \ No newline at end of file diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLi= b/PchSpi.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLi= b/PchSpi.c index aaf4e179..68031b4a 100644 --- a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSp= i.c +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSp= i.c @@ -9,7 +9,7 @@ #include =0D #include =0D #include =0D -#include =0D +#include =0D #include =0D #include =0D #include =0D diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLi= b/PeiSpiLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/Pei= SpiLib/PeiSpiLib.inf index c3bf6d02..e720eed2 100644 --- a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSp= iLib.inf +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSp= iLib.inf @@ -30,7 +30,7 @@ PchPciBdfLib [Packages]=0D MdePkg/MdePkg.dec=0D AlderlakeSiliconPkg/SiPkg.dec=0D -=0D +IntelSiliconPkg/IntelSiliconPkg.dec=0D =0D [Sources]=0D PchSpi.c=0D diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/B= aseSpiCommonLib/BaseSpiCommonLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Ip= Block/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf index 25ab9194..b38e149d 100644 --- a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiC= ommonLib/BaseSpiCommonLib.inf +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiC= ommonLib/BaseSpiCommonLib.inf @@ -19,11 +19,28 @@ [Packages]=0D MdePkg/MdePkg.dec=0D AlderlakeSiliconPkg/SiPkg.dec=0D + IntelSiliconPkg/IntelSiliconPkg.dec=0D =0D [LibraryClasses]=0D IoLib=0D DebugLib=0D PmcLib=0D PchPciBdfLib=0D + SpiAccessLib=0D =0D -[Pcd]=0D +[Guids]=0D + gFlashRegionDescriptorGuid=0D + gFlashRegionBiosGuid=0D + gFlashRegionMeGuid=0D + gFlashRegionGbeGuid=0D + gFlashRegionPlatformDataGuid=0D + gFlashRegionDerGuid=0D + gFlashRegionSecondaryBiosGuid=0D + gFlashRegionMicrocodePatchGuid=0D + gFlashRegionEcGuid=0D + gFlashRegionDeviceExpansionGuid=0D + gFlashRegionIeGuid=0D + gFlashRegion10GbeAGuid=0D + gFlashRegion10GbeBGuid=0D + gFlashRegionAllGuid=0D + gFlashRegionMaxGuid=0D diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/B= aseSpiCommonLib/SpiCommon.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi= /LibraryPrivate/BaseSpiCommonLib/SpiCommon.c index ab51521f..0890d498 100644 --- a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiC= ommonLib/SpiCommon.c +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiC= ommonLib/SpiCommon.c @@ -12,17 +12,137 @@ #include =0D #include =0D #include =0D -#include =0D +#include =0D #include =0D #include =0D #include =0D #include =0D #include =0D #include =0D +#include =0D =0D #define DEFAULT_CPU_STRAP_BASE_OFFSET 0x300 // Default CPU Straps base off= set=0D #define B_SPI_MEM_HSFSC_SAVE_MASK (B_SPI_MEM_HSFSC_FDBC_MASK | B_SPI_M= EM_HSFSC_CYCLE_MASK)=0D =0D +typedef enum {=0D + FlashRegionDescriptor,=0D + FlashRegionBios,=0D + FlashRegionMe,=0D + FlashRegionGbe,=0D + FlashRegionPlatformData,=0D + FlashRegionDer,=0D + FlashRegionSecondaryBios,=0D + FlashRegionMicrocodePatch,=0D + FlashRegionEc,=0D + FlashRegionDeviceExpansion,=0D + FlashRegionIe,=0D + FlashRegion10GbeA,=0D + FlashRegion10GbeB,=0D + FlashRegionAll =3D 16,=0D + FlashRegionMax=0D +} FLASH_REGION_TYPE;=0D +=0D +typedef struct {=0D + EFI_GUID *Guid;=0D + FLASH_REGION_TYPE Type;=0D +} FLASH_REGION_MAPPING;=0D +=0D +FLASH_REGION_MAPPING mFlashRegionTypes[] =3D {=0D + {=0D + &gFlashRegionDescriptorGuid,=0D + FlashRegionDescriptor=0D + },=0D + {=0D + &gFlashRegionBiosGuid,=0D + FlashRegionBios=0D + },=0D + {=0D + &gFlashRegionMeGuid,=0D + FlashRegionMe=0D + },=0D + {=0D + &gFlashRegionGbeGuid,=0D + FlashRegionGbe=0D + },=0D + {=0D + &gFlashRegionPlatformDataGuid,=0D + FlashRegionPlatformData=0D + },=0D + {=0D + &gFlashRegionDerGuid,=0D + FlashRegionDer=0D + },=0D + {=0D + &gFlashRegionSecondaryBiosGuid,=0D + FlashRegionSecondaryBios=0D + },=0D + {=0D + &gFlashRegionMicrocodePatchGuid,=0D + FlashRegionMicrocodePatch=0D + },=0D + {=0D + &gFlashRegionEcGuid,=0D + FlashRegionEc=0D + },=0D + {=0D + &gFlashRegionDeviceExpansionGuid,=0D + FlashRegionDeviceExpansion=0D + },=0D + {=0D + &gFlashRegionIeGuid,=0D + FlashRegionIe=0D + },=0D + {=0D + &gFlashRegion10GbeAGuid,=0D + FlashRegion10GbeA=0D + },=0D + {=0D + &gFlashRegion10GbeBGuid,=0D + FlashRegion10GbeB=0D + },=0D + {=0D + &gFlashRegionAllGuid,=0D + FlashRegionAll=0D + },=0D + {=0D + &gFlashRegionMaxGuid,=0D + FlashRegionMax=0D + }=0D +};=0D +=0D +/**=0D + Returns the type of a flash region given its GUID.=0D +=0D + @param[in] FlashRegionGuid Pointer to the flash region GUID.=0D + @param[out] FlashRegionType Pointer to a buffer that will be set to = the flash region type value.=0D +=0D + @retval EFI_SUCCESS The flash region type was found fo= r the given flash region GUID.=0D + @retval EFI_INVALID_PARAMETER A pointer argument passed to the f= unction is NULL.=0D + @retval EFI_NOT_FOUND The flash region type was not foun= d for the given flash region GUID.=0D +=0D +**/=0D +EFI_STATUS=0D +GetFlashRegionType (=0D + IN EFI_GUID *FlashRegionGuid,=0D + OUT FLASH_REGION_TYPE *FlashRegionType=0D + )=0D +{=0D + UINTN Index;=0D +=0D + if (FlashRegionGuid =3D=3D NULL || FlashRegionType =3D=3D NULL) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + for (Index =3D 0; Index < ARRAY_SIZE (mFlashRegionTypes); Index++) {=0D + if (CompareGuid (mFlashRegionTypes[Index].Guid, FlashRegionGuid)) {=0D + *FlashRegionType =3D mFlashRegionTypes[Index].Type;=0D + return EFI_SUCCESS;=0D + }=0D + }=0D +=0D + return EFI_NOT_FOUND;=0D +}=0D +=0D /**=0D Initialize an SPI protocol instance.=0D =0D @@ -184,7 +304,7 @@ SpiProtocolConstructor ( // If CPU Strap base address is different than 0x300 need to add MDTBA v= alue for final location=0D //=0D if (SpiInstance->CpuStrapBaseAddr !=3D DEFAULT_CPU_STRAP_BASE_OFFSET) {= =0D - Status =3D SpiProtocolFlashRead (&(SpiInstance->SpiProtocol), FlashReg= ionAll, R_FLASH_UMAP1, sizeof (Data32), (UINT8 *) (&Data32));=0D + Status =3D SpiProtocolFlashRead (&(SpiInstance->SpiProtocol), &gFlashR= egionAllGuid, R_FLASH_UMAP1, sizeof (Data32), (UINT8 *) (&Data32));=0D ASSERT_EFI_ERROR (Status);=0D Mdtba =3D (UINT16)(((Data32 & B_FLASH_UMAP1_MDTBA) >> N_FLASH_UMAP1_MD= TBA) << N_FLASH_UMAP1_MDTBA_REPR);=0D DEBUG ((DEBUG_INFO, "Mdtba : %0x\n", Mdtba));=0D @@ -279,7 +399,7 @@ PchPmTimerStallRuntimeSafe ( STATIC=0D BOOLEAN=0D WaitForSpiCycleComplete (=0D - IN PCH_SPI_PROTOCOL *This,=0D + IN PCH_SPI2_PROTOCOL *This,=0D IN UINTN PchSpiBar0,=0D IN BOOLEAN ErrorCheck=0D )=0D @@ -317,7 +437,7 @@ WaitForSpiCycleComplete ( This function waits for a pending SPI transaction to complete without cl= earing=0D status fields=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D @param[in] PchSpiBar0 SPI MMIO address=0D =0D @retval TRUE SPI cycle completed on the interface.=0D @@ -327,7 +447,7 @@ WaitForSpiCycleComplete ( BOOLEAN=0D STATIC=0D WaitForScipNoClear (=0D - IN PCH_SPI_PROTOCOL *This,=0D + IN PCH_SPI2_PROTOCOL *This,=0D IN UINTN PchSpiBar0=0D )=0D {=0D @@ -352,87 +472,11 @@ WaitForScipNoClear ( return FALSE;=0D }=0D =0D -/**=0D - This function sets the FDONE and optionally FCERR bits in the HSFS_CTL r= egister=0D -=0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D - @param[in] PchSpiBar0 SPI MMIO address=0D - @param[in] SetErrorBit Set to TRUE to set the FCERR bit=0D -=0D -**/=0D -VOID=0D -STATIC=0D -SetHsfscFdone (=0D - IN PCH_SPI_PROTOCOL *This,=0D - IN UINTN PchSpiBar0,=0D - IN BOOLEAN SetFcErrorBit=0D - )=0D -{=0D - EFI_STATUS Status;=0D - UINT32 HardwareSpiAddr;=0D - UINT32 FlashRegionSize;=0D - UINT32 Index;=0D - UINT8 DataCount;=0D -=0D - Status =3D SpiProtocolGetRegionAddress (This, FlashRegionBios, &Hardware= SpiAddr, &FlashRegionSize);=0D - if (EFI_ERROR (Status)) {=0D - return;=0D - }=0D -=0D - //=0D - // Clear FDONE and FCERR=0D - //=0D - MmioWrite8 (PchSpiBar0 + R_SPI_MEM_HSFSC, B_SPI_MEM_HSFSC_FCERR | B_SPI_= MEM_HSFSC_FDONE);=0D -=0D - //=0D - // Fill data buffer=0D - //=0D - if (SetFcErrorBit) {=0D - for (Index =3D 0; Index < 64; Index +=3D sizeof (UINT32)) {=0D - MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, 0xFFFFFFFF);=0D - }=0D - }=0D -=0D - //=0D - // Set the Flash Address=0D - //=0D - MmioWrite32 (=0D - (PchSpiBar0 + R_SPI_MEM_FADDR),=0D - (UINT32) (HardwareSpiAddr & B_SPI_MEM_FADDR_MASK)=0D - );=0D - //=0D - // Set Data count, Flash cycle, and Set Go bit to start a cycle=0D - //=0D - if (SetFcErrorBit) {=0D - DataCount =3D 0x3F;=0D - } else {=0D - DataCount =3D 0;=0D - }=0D - MmioAndThenOr32 (=0D - PchSpiBar0 + R_SPI_MEM_HSFSC,=0D - (UINT32) (~(B_SPI_MEM_HSFSC_FDBC_MASK | B_SPI_MEM_HSFSC_CYCLE_MASK)),= =0D - (UINT32) (((DataCount << N_SPI_MEM_HSFSC_FDBC) & B_SPI_MEM_HSFSC_FDBC_= MASK) |=0D - (V_SPI_MEM_HSFSC_CYCLE_READ << N_SPI_MEM_HSFSC_CYCLE) = |=0D - B_SPI_MEM_HSFSC_CYCLE_FGO)=0D - );=0D -=0D - if (SetFcErrorBit) {=0D - //=0D - // Intentionally write to FDATA while a cycle is in progress to genera= te an error=0D - //=0D - for (Index =3D 0; Index < 64; Index +=3D sizeof (UINT32)) {=0D - MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, 0x0);=0D - }=0D - }=0D -=0D - WaitForScipNoClear (This, PchSpiBar0);=0D -}=0D -=0D /**=0D This function sends the programmed SPI command to the device.=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D - @param[in] SpiRegionType The SPI Region type for flash cycle whic= h is listed in the Descriptor=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D + @param[in] FlashRegionGuid The Flash Region GUID for flash cycle wh= ich corresponds to the type in the descriptor.=0D @param[in] FlashCycleType The Flash SPI cycle type list in HSFC (H= ardware Sequencing Flash Control Register) register=0D @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions.=0D @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle.=0D @@ -446,8 +490,8 @@ SetHsfscFdone ( STATIC=0D EFI_STATUS=0D SendSpiCmd (=0D - IN PCH_SPI_PROTOCOL *This,=0D - IN FLASH_REGION_TYPE FlashRegionType,=0D + IN PCH_SPI2_PROTOCOL *This,=0D + IN EFI_GUID *FlashRegionGuid,=0D IN FLASH_CYCLE_TYPE FlashCycleType,=0D IN UINT32 Address,=0D IN UINT32 ByteCount,=0D @@ -564,7 +608,7 @@ SendSpiCmd ( }=0D }=0D =0D - Status =3D SpiProtocolGetRegionAddress (This, FlashRegionType, &Hardware= SpiAddr, &FlashRegionSize);=0D + Status =3D SpiProtocolGetRegionAddress (This, FlashRegionGuid, &Hardware= SpiAddr, &FlashRegionSize);=0D if (EFI_ERROR (Status)) {=0D goto SendSpiCmdEnd;=0D }=0D @@ -751,31 +795,6 @@ SendSpiCmd ( } while (ByteCount > 0);=0D =0D SendSpiCmdEnd:=0D - //=0D - // Restore SPI controller state=0D - //=0D - if (RestoreState) {=0D - if (HsfscFdoneSave) {=0D - SetHsfscFdone (This, PchSpiBar0, HsfscFcerrSave);=0D - }=0D - MmioAndThenOr32 (=0D - PchSpiBar0 + R_SPI_MEM_HSFSC,=0D - (UINT32) ~(B_SPI_MEM_HSFSC_SAVE_MASK |=0D - B_SPI_MEM_HSFSC_SAF_CE | // This bit clears when se= t to 1, ensure 0 is written=0D - B_SPI_MEM_HSFSC_SAF_LE | // This bit clears when se= t to 1, ensure 0 is written=0D - B_SPI_MEM_HSFSC_SAF_DLE | // This bit clears when se= t to 1, ensure 0 is written=0D - B_SPI_MEM_HSFSC_SAF_ERROR | // This bit clears when se= t to 1, ensure 0 is written=0D - B_SPI_MEM_HSFSC_AEL | // This bit clears when se= t to 1, ensure 0 is written=0D - B_SPI_MEM_HSFSC_FCERR | // This bit clears when se= t to 1, ensure 0 is written=0D - B_SPI_MEM_HSFSC_FDONE), // This bit clears when se= t to 1, ensure 0 is written=0D - HsfscSave=0D - );=0D - MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FADDR, FaddrSave);=0D - for (Index =3D 0; Index < 64; Index +=3D sizeof (UINT32)) {=0D - MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, FdataSave[Index= >> 2]);=0D - }=0D - }=0D -=0D //=0D // Restore the settings for SPI Prefetching and Caching and enable BIOS = Write Protect=0D //=0D @@ -801,8 +820,8 @@ SendSpiCmdEnd: /**=0D Read data from the flash part.=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D - @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor.=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D + @param[in] FlashRegionGuid The Flash Region GUID for flash cycle wh= ich corresponds to the type in the descriptor.=0D @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions.=0D @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle.=0D @param[out] Buffer The Pointer to caller-allocated buffer c= ontaining the dada received.=0D @@ -815,8 +834,8 @@ SendSpiCmdEnd: EFI_STATUS=0D EFIAPI=0D SpiProtocolFlashRead (=0D - IN PCH_SPI_PROTOCOL *This,=0D - IN FLASH_REGION_TYPE FlashRegionType,=0D + IN PCH_SPI2_PROTOCOL *This,=0D + IN EFI_GUID *FlashRegionGuid,=0D IN UINT32 Address,=0D IN UINT32 ByteCount,=0D OUT UINT8 *Buffer=0D @@ -829,7 +848,7 @@ SpiProtocolFlashRead ( //=0D Status =3D SendSpiCmd (=0D This,=0D - FlashRegionType,=0D + FlashRegionGuid,=0D FlashCycleRead,=0D Address,=0D ByteCount,=0D @@ -841,8 +860,8 @@ SpiProtocolFlashRead ( /**=0D Write data to the flash part.=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D - @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor.=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D + @param[in] FlashRegionGuid The Flash Region GUID for flash cycle wh= ich corresponds to the type in the descriptor.=0D @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions.=0D @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle.=0D @param[in] Buffer Pointer to caller-allocated buffer conta= ining the data sent during the SPI cycle.=0D @@ -854,8 +873,8 @@ SpiProtocolFlashRead ( EFI_STATUS=0D EFIAPI=0D SpiProtocolFlashWrite (=0D - IN PCH_SPI_PROTOCOL *This,=0D - IN FLASH_REGION_TYPE FlashRegionType,=0D + IN PCH_SPI2_PROTOCOL *This,=0D + IN EFI_GUID *FlashRegionGuid,=0D IN UINT32 Address,=0D IN UINT32 ByteCount,=0D IN UINT8 *Buffer=0D @@ -868,7 +887,7 @@ SpiProtocolFlashWrite ( //=0D Status =3D SendSpiCmd (=0D This,=0D - FlashRegionType,=0D + FlashRegionGuid,=0D FlashCycleWrite,=0D Address,=0D ByteCount,=0D @@ -880,8 +899,8 @@ SpiProtocolFlashWrite ( /**=0D Erase some area on the flash part.=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D - @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor.=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D + @param[in] FlashRegionGuid The Flash Region GUID for flash cycle wh= ich corresponds to the type in the descriptor.=0D @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions.=0D @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle.=0D =0D @@ -892,8 +911,8 @@ SpiProtocolFlashWrite ( EFI_STATUS=0D EFIAPI=0D SpiProtocolFlashErase (=0D - IN PCH_SPI_PROTOCOL *This,=0D - IN FLASH_REGION_TYPE FlashRegionType,=0D + IN PCH_SPI2_PROTOCOL *This,=0D + IN EFI_GUID *FlashRegionGuid,=0D IN UINT32 Address,=0D IN UINT32 ByteCount=0D )=0D @@ -905,7 +924,7 @@ SpiProtocolFlashErase ( //=0D Status =3D SendSpiCmd (=0D This,=0D - FlashRegionType,=0D + FlashRegionGuid,=0D FlashCycleErase,=0D Address,=0D ByteCount,=0D @@ -917,7 +936,7 @@ SpiProtocolFlashErase ( /**=0D Read SFDP data from the flash part.=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D @param[in] ComponentNumber The Componen Number for chip select=0D @param[in] Address The starting byte address for SFDP data = read.=0D @param[in] ByteCount Number of bytes in SFDP data portion of = the SPI cycle=0D @@ -932,20 +951,53 @@ SpiProtocolFlashErase ( EFI_STATUS=0D EFIAPI=0D SpiProtocolFlashReadSfdp (=0D - IN PCH_SPI_PROTOCOL *This,=0D + IN PCH_SPI2_PROTOCOL *This,=0D IN UINT8 ComponentNumber,=0D IN UINT32 Address,=0D IN UINT32 ByteCount,=0D OUT UINT8 *SfdpData=0D )=0D {=0D - return EFI_SUCCESS;=0D + SPI_INSTANCE *SpiInstance;=0D + EFI_STATUS Status;=0D + UINT32 FlashAddress;=0D +=0D + if (SpiIsSafModeActive ()) {=0D + DEBUG ((DEBUG_ERROR, "Unallowed call to %a while SAF Mode is active.\n= ", __FUNCTION__));=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + SpiInstance =3D SPI_INSTANCE_FROM_SPIPROTOCOL (This);=0D + Status =3D EFI_SUCCESS;=0D +=0D + if (ComponentNumber > SpiInstance->NumberOfComponents) {=0D + ASSERT (FALSE);=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + FlashAddress =3D 0;=0D + if (ComponentNumber =3D=3D FlashComponent1) {=0D + FlashAddress =3D SpiInstance->Component1StartAddr;=0D + }=0D + FlashAddress +=3D Address;=0D + //=0D + // Sends the command to the SPI interface to execute.=0D + //=0D + Status =3D SendSpiCmd (=0D + This,=0D + &gFlashRegionAllGuid,=0D + FlashCycleReadSfdp,=0D + FlashAddress,=0D + ByteCount,=0D + SfdpData=0D + );=0D + return Status;=0D }=0D =0D /**=0D Read Jedec Id from the flash part.=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D @param[in] ComponentNumber The Componen Number for chip select=0D @param[in] ByteCount Number of bytes in JedecId data portion = of the SPI cycle, the data size is 3 typically=0D @param[out] JedecId The Pointer to caller-allocated buffer c= ontaining JEDEC ID received=0D @@ -959,19 +1011,52 @@ SpiProtocolFlashReadSfdp ( EFI_STATUS=0D EFIAPI=0D SpiProtocolFlashReadJedecId (=0D - IN PCH_SPI_PROTOCOL *This,=0D + IN PCH_SPI2_PROTOCOL *This,=0D IN UINT8 ComponentNumber,=0D IN UINT32 ByteCount,=0D OUT UINT8 *JedecId=0D )=0D {=0D - return EFI_SUCCESS;=0D + SPI_INSTANCE *SpiInstance;=0D + EFI_STATUS Status;=0D + UINT32 Address;=0D +=0D + if (SpiIsSafModeActive ()) {=0D + DEBUG ((DEBUG_ERROR, "Unallowed call to %a while SAF Mode is active.\n= ", __FUNCTION__));=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + SpiInstance =3D SPI_INSTANCE_FROM_SPIPROTOCOL (This);=0D + Status =3D EFI_SUCCESS;=0D +=0D + if (ComponentNumber > SpiInstance->NumberOfComponents) {=0D + ASSERT (FALSE);=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + Address =3D 0;=0D + if (ComponentNumber =3D=3D FlashComponent1) {=0D + Address =3D SpiInstance->Component1StartAddr;=0D + }=0D +=0D + //=0D + // Sends the command to the SPI interface to execute.=0D + //=0D + Status =3D SendSpiCmd (=0D + This,=0D + &gFlashRegionAllGuid,=0D + FlashCycleReadJedecId,=0D + Address,=0D + ByteCount,=0D + JedecId=0D + );=0D + return Status;=0D }=0D =0D /**=0D Write the status register in the flash part.=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically=0D @param[in] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register writing=0D =0D @@ -983,18 +1068,36 @@ SpiProtocolFlashReadJedecId ( EFI_STATUS=0D EFIAPI=0D SpiProtocolFlashWriteStatus (=0D - IN PCH_SPI_PROTOCOL *This,=0D + IN PCH_SPI2_PROTOCOL *This,=0D IN UINT32 ByteCount,=0D IN UINT8 *StatusValue=0D )=0D {=0D - return EFI_SUCCESS;=0D + EFI_STATUS Status;=0D +=0D + if (SpiIsSafModeActive ()) {=0D + DEBUG ((DEBUG_ERROR, "Unallowed call to %a while SAF Mode is active.\n= ", __FUNCTION__));=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + //=0D + // Sends the command to the SPI interface to execute.=0D + //=0D + Status =3D SendSpiCmd (=0D + This,=0D + &gFlashRegionAllGuid,=0D + FlashCycleWriteStatus,=0D + 0,=0D + ByteCount,=0D + StatusValue=0D + );=0D + return Status;=0D }=0D =0D /**=0D Read status register in the flash part.=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically=0D @param[out] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register received.=0D =0D @@ -1006,19 +1109,37 @@ SpiProtocolFlashWriteStatus ( EFI_STATUS=0D EFIAPI=0D SpiProtocolFlashReadStatus (=0D - IN PCH_SPI_PROTOCOL *This,=0D + IN PCH_SPI2_PROTOCOL *This,=0D IN UINT32 ByteCount,=0D OUT UINT8 *StatusValue=0D )=0D {=0D - return EFI_SUCCESS;=0D + EFI_STATUS Status;=0D +=0D + if (SpiIsSafModeActive ()) {=0D + DEBUG ((DEBUG_ERROR, "Unallowed call to %a while SAF Mode is active.\n= ", __FUNCTION__));=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + //=0D + // Sends the command to the SPI interface to execute.=0D + //=0D + Status =3D SendSpiCmd (=0D + This,=0D + &gFlashRegionAllGuid,=0D + FlashCycleReadStatus,=0D + 0,=0D + ByteCount,=0D + StatusValue=0D + );=0D + return Status;=0D }=0D =0D /**=0D Get the SPI region base and size, based on the enum type=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D - @param[in] FlashRegionType The Flash Region type for for the base a= ddress which is listed in the Descriptor.=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D + @param[in] FlashRegionGuid The Flash Region GUID for flash cycle wh= ich corresponds to the type in the descriptor.=0D @param[out] BaseAddress The Flash Linear Address for the Region = 'n' Base=0D @param[out] RegionSize The size for the Region 'n'=0D =0D @@ -1029,18 +1150,24 @@ SpiProtocolFlashReadStatus ( EFI_STATUS=0D EFIAPI=0D SpiProtocolGetRegionAddress (=0D - IN PCH_SPI_PROTOCOL *This,=0D - IN FLASH_REGION_TYPE FlashRegionType,=0D + IN PCH_SPI2_PROTOCOL *This,=0D + IN EFI_GUID *FlashRegionGuid,=0D OUT UINT32 *BaseAddress,=0D OUT UINT32 *RegionSize=0D )=0D {=0D + EFI_STATUS Status;=0D + FLASH_REGION_TYPE FlashRegionType;=0D SPI_INSTANCE *SpiInstance;=0D UINTN PchSpiBar0;=0D UINT32 ReadValue;=0D =0D SpiInstance =3D SPI_INSTANCE_FROM_SPIPROTOCOL (This);=0D =0D + Status =3D GetFlashRegionType (FlashRegionGuid, &FlashRegionType);=0D + if (EFI_ERROR (Status)) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D if (FlashRegionType >=3D FlashRegionMax) {=0D return EFI_INVALID_PARAMETER;=0D }=0D @@ -1053,10 +1180,13 @@ SpiProtocolGetRegionAddress ( =0D PchSpiBar0 =3D AcquireSpiBar0 (SpiInstance);=0D =0D - ReadValue =3D MmioRead32 (PchSpiBar0 + (R_SPI_MEM_FREG0_FLASHD + (S_SPI_= MEM_FREGX * ((UINT32) FlashRegionType))));=0D + if (((MmioRead32 (PchSpiBar0 + R_SPI_MEM_BFPR) & B_SPI_MEM_BFPR_SBRS) != =3D 0) &&=0D + (FlashRegionType =3D=3D FlashRegionBios)) {=0D + FlashRegionType =3D FlashRegionSecondaryBios;=0D + }=0D =0D ReleaseSpiBar0 (SpiInstance);=0D -=0D + ReadValue =3D MmioRead32 (PchSpiBar0 + (R_SPI_MEM_FREG0_FLASHD + (S_SPI_= MEM_FREGX * ((UINT32) FlashRegionType))));=0D //=0D // If the region is not used, the Region Base is 7FFFh and Region Limit = is 0000h=0D //=0D @@ -1077,7 +1207,7 @@ SpiProtocolGetRegionAddress ( /**=0D Read PCH Soft Strap Values=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA= .=0D @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle=0D @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining PCH Soft Strap Value.=0D @@ -1091,19 +1221,51 @@ SpiProtocolGetRegionAddress ( EFI_STATUS=0D EFIAPI=0D SpiProtocolReadPchSoftStrap (=0D - IN PCH_SPI_PROTOCOL *This,=0D + IN PCH_SPI2_PROTOCOL *This,=0D IN UINT32 SoftStrapAddr,=0D IN UINT32 ByteCount,=0D OUT VOID *SoftStrapValue=0D )=0D {=0D - return EFI_SUCCESS;=0D + SPI_INSTANCE *SpiInstance;=0D + UINT32 StrapFlashAddr;=0D + EFI_STATUS Status;=0D +=0D + SpiInstance =3D SPI_INSTANCE_FROM_SPIPROTOCOL (This);=0D +=0D + if (ByteCount =3D=3D 0) {=0D + *(UINT16 *) SoftStrapValue =3D SpiInstance->PchStrapSize;=0D + return EFI_SUCCESS;=0D + }=0D +=0D + if ((SoftStrapAddr + ByteCount) > (UINT32) SpiInstance->PchStrapSize) {= =0D + ASSERT (FALSE);=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + //=0D + // PCH Strap Flash Address =3D FPSBA + RamAddr=0D + //=0D + StrapFlashAddr =3D SpiInstance->PchStrapBaseAddr + SoftStrapAddr;=0D +=0D + //=0D + // Read PCH Soft straps from using execute command=0D + //=0D + Status =3D SendSpiCmd (=0D + This,=0D + &gFlashRegionDescriptorGuid,=0D + FlashCycleRead,=0D + StrapFlashAddr,=0D + ByteCount,=0D + SoftStrapValue=0D + );=0D + return Status;=0D }=0D =0D /**=0D Read CPU Soft Strap Values=0D =0D - @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] This Pointer to the PCH_SPI2_PROTOCOL instanc= e.=0D @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUS= BA.=0D @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle.=0D @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining CPU Soft Strap Value.=0D @@ -1117,11 +1279,43 @@ SpiProtocolReadPchSoftStrap ( EFI_STATUS=0D EFIAPI=0D SpiProtocolReadCpuSoftStrap (=0D - IN PCH_SPI_PROTOCOL *This,=0D + IN PCH_SPI2_PROTOCOL *This,=0D IN UINT32 SoftStrapAddr,=0D IN UINT32 ByteCount,=0D OUT VOID *SoftStrapValue=0D )=0D {=0D - return EFI_SUCCESS;=0D + SPI_INSTANCE *SpiInstance;=0D + UINT32 StrapFlashAddr;=0D + EFI_STATUS Status;=0D +=0D + SpiInstance =3D SPI_INSTANCE_FROM_SPIPROTOCOL (This);=0D +=0D + if (ByteCount =3D=3D 0) {=0D + *(UINT16 *) SoftStrapValue =3D SpiInstance->CpuStrapSize;=0D + return EFI_SUCCESS;=0D + }=0D +=0D + if ((SoftStrapAddr + ByteCount) > (UINT32) SpiInstance->CpuStrapSize) {= =0D + ASSERT (FALSE);=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + //=0D + // CPU Strap Flash Address =3D FCPUSBA + RamAddr=0D + //=0D + StrapFlashAddr =3D SpiInstance->CpuStrapBaseAddr + SoftStrapAddr;=0D +=0D + //=0D + // Read Cpu Soft straps from using execute command=0D + //=0D + Status =3D SendSpiCmd (=0D + This,=0D + &gFlashRegionDescriptorGuid,=0D + FlashCycleRead,=0D + StrapFlashAddr,=0D + ByteCount,=0D + SoftStrapValue=0D + );=0D + return Status;=0D }=0D diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c b/Sili= con/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c index 2dd80eba..164f017c 100644 --- a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c @@ -13,10 +13,11 @@ #include =0D #include =0D #include =0D -#include =0D +#include =0D #include =0D #include =0D #include =0D +#include =0D #include =0D #include =0D #include =0D @@ -82,8 +83,8 @@ SpiExitBootServicesCallback ( - Documented in System Management Mode Core Interface Specification = .=0D =0D - @result=0D - The SPI SMM driver produces @link _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL @= endlink with GUID=0D - gPchSmmSpiProtocolGuid which is different from SPI RUNTIME driver.=0D + The SPI SMM driver produces @link _PCH_SPI2_PROTOCOL PCH_SPI2_PROTOCOL= @endlink with GUID=0D + gPchSmmSpi2ProtocolGuid which is different from SPI RUNTIME driver.=0D =0D - Integration Check List\n=0D - This driver supports Descriptor Mode only.=0D @@ -163,11 +164,11 @@ InstallPchSpi ( }=0D =0D //=0D - // Install the SMM PCH_SPI_PROTOCOL interface=0D + // Install the SMM PCH_SPI2_PROTOCOL interface=0D //=0D Status =3D gSmst->SmmInstallProtocolInterface (=0D &(mSpiInstance->Handle),=0D - &gPchSmmSpiProtocolGuid,=0D + &gPchSmmSpi2ProtocolGuid,=0D EFI_NATIVE_INTERFACE,=0D &(mSpiInstance->SpiProtocol)=0D );=0D @@ -303,6 +304,23 @@ DisableBiosWriteProtect ( B_SPI_CFG_BC_WPD=0D );=0D =0D + ///=0D + /// PCH BIOS Spec Section 3.7 BIOS Region SMM Protection Enabling=0D + /// If the following steps are implemented:=0D + /// - Set the EISS bit (SPI PCI Offset DCh [5]) =3D 1b=0D + /// - Follow the 1st recommendation in section 3.6=0D + /// the BIOS Region can only be updated by following the steps bellow:=0D + /// - Once all threads enter SMM=0D + /// - Read memory location FED30880h OR with 00000001h, place the resul= t in EAX,=0D + /// and write data to lower 32 bits of MSR 1FEh (sample code availabl= e)=0D + /// - Set BIOSWE bit (SPI PCI Offset DCh [0]) =3D 1b=0D + /// - Modify BIOS Region=0D + /// - Clear BIOSWE bit (SPI PCI Offset DCh [0]) =3D 0b=0D + ///=0D + if ((PciSegmentRead8 (SpiBaseAddress + R_SPI_CFG_BC) & B_SPI_CFG_BC_EISS= ) !=3D 0) {=0D + PchSetInSmmSts ();=0D + }=0D +=0D return EFI_SUCCESS;=0D }=0D =0D @@ -327,6 +345,12 @@ EnableBiosWriteProtect ( (UINT8) (~B_SPI_CFG_BC_WPD)=0D );=0D =0D + ///=0D + /// Check if EISS bit is set=0D + ///=0D + if (((PciSegmentRead8 (SpiBaseAddress + R_SPI_CFG_BC)) & B_SPI_CFG_BC_EI= SS) =3D=3D B_SPI_CFG_BC_EISS) {=0D + PchClearInSmmSts ();=0D + }=0D }=0D =0D /**=0D diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf b= /Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf index 78913423..445f4af8 100644 --- a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf @@ -24,19 +24,20 @@ UefiBootServicesTableLib BaseLib=0D SmmServicesTableLib=0D SpiCommonLib=0D +SmmPchPrivateLib=0D PchPciBdfLib=0D =0D [Packages]=0D MdePkg/MdePkg.dec=0D AlderlakeSiliconPkg/SiPkg.dec=0D -=0D +IntelSiliconPkg/IntelSiliconPkg.dec=0D =0D [Sources]=0D Spi.c=0D =0D =0D [Protocols]=0D -gPchSmmSpiProtocolGuid ## PRODUCES=0D +gPchSmmSpi2ProtocolGuid ## PRODUCES=0D gEfiSmmCpuProtocolGuid ## CONSUMES=0D gEdkiiSmmExitBootServicesProtocolGuid ## CONSUMES=0D =0D diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/IncludePrivate/Library/S= mmPchPrivateLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Pch/IncludePrivate/Li= brary/SmmPchPrivateLib.h new file mode 100644 index 00000000..63857863 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/IncludePrivate/Library/SmmPchPr= ivateLib.h @@ -0,0 +1,27 @@ +/** @file=0D + Header file for private PCH SMM Lib.=0D +=0D + Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +#ifndef _SMM_PCH_PRIVATE_LIB_H_=0D +#define _SMM_PCH_PRIVATE_LIB_H_=0D +=0D +/**=0D + Set InSmm.Sts bit=0D +**/=0D +VOID=0D +PchSetInSmmSts (=0D + VOID=0D + );=0D +=0D +/**=0D + Clear InSmm.Sts bit=0D +**/=0D +VOID=0D +PchClearInSmmSts (=0D + VOID=0D + );=0D +=0D +#endif // _SMM_PCH_PRIVATE_LIB_H_=0D diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPri= vateLib/SmmPchPrivateLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Pch/LibraryP= rivate/SmmPchPrivateLib/SmmPchPrivateLib.c new file mode 100644 index 00000000..bdb2283d --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPrivateLib= /SmmPchPrivateLib.c @@ -0,0 +1,83 @@ +/** @file=0D + PCH SMM private lib.=0D +=0D + Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +=0D +/**=0D + Set InSmm.Sts bit=0D +**/=0D +VOID=0D +PchSetInSmmSts (=0D + VOID=0D + )=0D +{=0D + UINT32 Data32;=0D +=0D + ///=0D + /// If platform disables TXT_PTLEN strap, NL socket(s) will target abort= =0D + /// when trying to access LT register space below, and writes to=0D + /// NL's MSR 0x1FE will GP fault. Check straps enabled first.=0D + ///=0D +=0D + Data32 =3D MmioRead32 (R_LT_EXISTS);=0D +=0D + if (Data32 =3D=3D 0xFFFFFFFF) {=0D + return;=0D + }=0D + ///=0D + /// Read memory location FED30880h OR with 00000001h, place the result i= n EAX,=0D + /// and write data to lower 32 bits of MSR 1FEh (sample code available)= =0D + ///=0D + Data32 =3D MmioRead32 (R_LT_UCS);=0D + AsmWriteMsr32 (MSR_SPCL_CHIPSET_USAGE, Data32 | BIT0);=0D + ///=0D + /// Read FED30880h back to ensure the setting went through.=0D + ///=0D + Data32 =3D MmioRead32 (R_LT_UCS);=0D +}=0D +=0D +/**=0D + Clear InSmm.Sts bit=0D +**/=0D +VOID=0D +PchClearInSmmSts (=0D + VOID=0D + )=0D +{=0D + UINT32 Data32;=0D +=0D + ///=0D + /// If platform disables TXT_PTLEN strap, NL socket(s) will target abort= =0D + /// when trying to access LT register space below, and writes to=0D + /// NL's MSR 0x1FE will GP fault. Check straps enabled first.=0D + ///=0D +=0D + Data32 =3D MmioRead32 (R_LT_EXISTS);=0D + if (Data32 =3D=3D 0xFFFFFFFF) {=0D + return;=0D + }=0D +=0D + ///=0D + /// Read memory location FED30880h AND with FFFFFFFEh, place the result = in EAX,=0D + /// and write data to lower 32 bits of MSR 1FEh (sample code available)= =0D + ///=0D + Data32 =3D MmioRead32 (R_LT_UCS);=0D + AsmWriteMsr32 (MSR_SPCL_CHIPSET_USAGE, Data32 & (UINT32) (~BIT0));=0D + ///=0D + /// Read FED30880h back to ensure the setting went through.=0D + ///=0D + Data32 =3D MmioRead32 (R_LT_UCS);=0D +}=0D diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPri= vateLib/SmmPchPrivateLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Librar= yPrivate/SmmPchPrivateLib/SmmPchPrivateLib.inf new file mode 100644 index 00000000..3c62b9b8 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPrivateLib= /SmmPchPrivateLib.inf @@ -0,0 +1,32 @@ +## @file=0D +# PCH SMM private lib.=0D +#=0D +# Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D SmmPchPrivateLib=0D +FILE_GUID =3D FE6495FB-7AA9-4A24-BF3E-4698F7BCE0EE=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D DXE_SMM_DRIVER=0D +LIBRARY_CLASS =3D SmmPchPrivateLib=0D +=0D +=0D +[LibraryClasses]=0D +BaseLib=0D +IoLib=0D +DebugLib=0D +CpuPlatformLib=0D +=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +AlderlakeSiliconPkg/SiPkg.dec=0D +=0D +=0D +[Sources]=0D +SmmPchPrivateLib.c=0D diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLi= b.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc index 37876cbf..238473c2 100644 --- a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc +++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc @@ -11,6 +11,11 @@ !include $(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/DxeLib.dsc=0D !include $(PLATFORM_SI_PACKAGE)/Fru/AdlPch/DxeLib.dsc=0D =0D +#=0D +# Pch=0D +#=0D + SmmPchPrivateLib|$(PLATFORM_SI_PACKAGE)/Pch/LibraryPrivate/SmmPchPrivateL= ib/SmmPchPrivateLib.inf=0D +=0D #=0D # Common=0D #=0D diff --git a/Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec b/Silicon/Intel/Al= derlakeSiliconPkg/SiPkg.dec index ce9cfe59..4871a014 100644 --- a/Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec +++ b/Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec @@ -33,6 +33,7 @@ IpBlock/HostBridge/IncludePrivate =0D # Cpu=0D Cpu/IncludePrivate=0D +Pch/IncludePrivate=0D =0D IncludePrivate=0D =0D @@ -93,6 +94,8 @@ Include/ConfigBlock/Wdt Include/ConfigBlock/PcieRp/PchPcieRp=0D Include/ConfigBlock/PcieRp=0D Include/ConfigBlock/SerialIo=0D +Include/ConfigBlock/Usb=0D +=0D =0D [Guids.common.Private]=0D #=0D @@ -193,6 +196,7 @@ gPcieRpPreMemConfigGuid =3D {0x8377AB38, 0xF8B0, 0x47= 6A, { 0x9C, 0xA1, 0x68, 0xE gSmbusPreMemConfigGuid =3D {0x77A6E62C, 0x716B, 0x4386, {0x9E, 0x9C, 0x2= 3, 0xA0, 0x2E, 0x13, 0x7B, 0x3A}}=0D gLpcPreMemConfigGuid =3D {0xA6E6032F, 0x1E58, 0x407E, {0x9A, 0xB8, 0xC6,= 0x30, 0xC6, 0xC4, 0x11, 0x8E}}=0D gPchDmiPreMemConfigGuid =3D {0x4DA4AA22, 0xB54A, 0x43D7, {0x87, 0xC8, 0x= A3, 0xCF, 0x53, 0xE6, 0xC1, 0x8A}}=0D +gUsbConfigGuid =3D {0xB2DA9CCD, 0x6A8C, 0x4BB6, {0xB3, 0xE6, 0xCD, 0xFB,= 0xB7, 0x66, 0x8B, 0xDE}}=0D =0D gPchGeneralConfigGuid =3D {0x6ED94C8C, 0x25F7, 0x4686, {0xB2, 0x46, 0xCA= , 0x4D, 0xE2, 0x95, 0x4B, 0x5D}}=0D gPchPcieConfigGuid =3D {0x0A53B507, 0x988B, 0x475C, {0xBF, 0x76, 0x33, 0= xDE, 0x10, 0x6D, 0x94, 0x84}}=0D @@ -355,6 +359,7 @@ PchInfoLib|Pch/Include/Library/PchInfoLib.h PchPcieRpLib|Include/Library/PchPcieRpLib.h=0D PchPcrLib|Include/Library/PchPcrLib.h=0D PchSbiAccessLib|IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h=0D +SmmPchPrivateLib|Pch/IncludePrivate/Library/SmmPchPrivateLib.h=0D PchPciBdfLib|Pch/Include/Library/PchPciBdfLib.h=0D PchRasLib|Pch/Include/Library/PchRasLib.h=0D PchRtcLib|Pch/Include/Library/PchRtcLib.h=0D @@ -394,7 +399,7 @@ OcPlatformLib|Include/Library/OcPlatformLib.h PeiSpsPreMemPolicyLib|Include/Library/PeiSpsPreMemPolicyLib.h=0D PmcLib|Include/Library/PmcLib.h=0D PmcSsramLib|Include/Library/PmcSsramLib.h=0D -SpiLib|Include/Library/SpiLib.h=0D +SpiAccessLib|Include/Library/SpiAccessLib.h=0D SpsDxeLib|Include/Library/SpsDxeLib.h=0D SpsGetDxeConfigBlockLib|Include/Library/SpsGetDxeConfigBlock.h=0D MeGetPeiConfigBlock|Include/Library/MeGetConfigBlock.h=0D --=20 2.26.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#115051): https://edk2.groups.io/g/devel/message/115051 Mute This Topic: https://groups.io/mt/104120129/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-