From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web12.90681.1638360143585272139 for ; Wed, 01 Dec 2021 04:02:24 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: sebastien.boeuf@intel.com) X-IronPort-AV: E=McAfee;i="6200,9189,10184"; a="322689213" X-IronPort-AV: E=Sophos;i="5.87,278,1631602800"; d="scan'208";a="322689213" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2021 04:02:18 -0800 X-IronPort-AV: E=Sophos;i="5.87,278,1631602800"; d="scan'208";a="596306870" Received: from rshussey-mobl1.ger.corp.intel.com (HELO sboeuf-mobl.home) ([10.252.26.82]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2021 04:02:14 -0800 From: sebastien.boeuf@intel.com To: devel@edk2.groups.io Cc: jiewen.yao@intel.com, jordan.l.justen@intel.com, kraxel@redhat.com, sebastien.boeuf@intel.com Subject: [PATCH 1/5] OvmfPkg: Handle Cloud Hypervisor host bridge Date: Wed, 1 Dec 2021 13:01:44 +0100 Message-Id: <699f8ae9384b47d66f35f3ab939014190049cdab.1638351613.git.sebastien.boeuf@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable From: Sebastien Boeuf Handle things differently when the detected host bridge matches the Cloud Hypervisor PCI host bridge identifier. Signed-off-by: Rob Bradford Signed-off-by: Sebastien Boeuf --- OvmfPkg/Csm/CsmSupportLib/LegacyInterrupt.c | 1 + OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c | 1 + OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h | 1 + OvmfPkg/Include/IndustryStandard/CloudHv.h | 35 +++++++++++ OvmfPkg/Include/OvmfPlatforms.h | 1 + .../Library/AcpiTimerLib/BaseAcpiTimerLib.c | 3 + .../AcpiTimerLib/BaseRomAcpiTimerLib.c | 4 ++ .../Library/AcpiTimerLib/DxeAcpiTimerLib.c | 3 + .../PlatformBootManagerLib/BdsPlatform.c | 1 + .../ResetSystemLib/BaseResetShutdown.c | 3 + .../Library/ResetSystemLib/DxeResetShutdown.c | 11 +++- OvmfPkg/PlatformPei/MemDetect.c | 63 ++++++++++--------- OvmfPkg/PlatformPei/Platform.c | 11 +++- 13 files changed, 105 insertions(+), 33 deletions(-) create mode 100644 OvmfPkg/Include/IndustryStandard/CloudHv.h diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyInterrupt.c b/OvmfPkg/Csm/CsmS= upportLib/LegacyInterrupt.c index 97ca21945f..50c9322911 100644 --- a/OvmfPkg/Csm/CsmSupportLib/LegacyInterrupt.c +++ b/OvmfPkg/Csm/CsmSupportLib/LegacyInterrupt.c @@ -189,6 +189,7 @@ LegacyInterruptInstall ( mLegacyInterruptDevice =3D LEGACY_INT_DEV_PIIX4; break; case INTEL_Q35_MCH_DEVICE_ID: + case CLOUDHV_DEVICE_ID: // Cloud Hypervisor host bridge mLegacyInterruptDevice =3D LEGACY_INT_DEV_Q35; break; default: diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c b/OvmfPkg/Csm/CsmSupp= ortLib/LegacyRegion.c index fe9ae27c9d..9d6d6faf48 100644 --- a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c +++ b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c @@ -474,6 +474,7 @@ LegacyRegionInit ( mRegisterValues =3D mRegisterValues440; break; case INTEL_Q35_MCH_DEVICE_ID: + case CLOUDHV_DEVICE_ID: // Cloud Hypervisor host bridge mRegisterValues =3D mRegisterValuesQ35; break; default: diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h b/OvmfPkg/Csm/CsmSupp= ortLib/LegacyRegion.h index e18cb97949..71df8f5fb2 100644 --- a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h +++ b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h @@ -17,6 +17,7 @@ #include #include #include +#include = #include #include diff --git a/OvmfPkg/Include/IndustryStandard/CloudHv.h b/OvmfPkg/Include/I= ndustryStandard/CloudHv.h new file mode 100644 index 0000000000..6ab18ad50d --- /dev/null +++ b/OvmfPkg/Include/IndustryStandard/CloudHv.h @@ -0,0 +1,35 @@ +/** @file + Various defines related to Cloud Hypervisor + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef __CLOUDHV_H__ +#define __CLOUDHV_H__ + +// +// Host Bridge Device ID +// +#define CLOUDHV_DEVICE_ID 0x0d57 + +// +// ACPI timer address +// +#define CLOUDHV_ACPI_TIMER_IO_ADDRESS 0xb008 + +// +// ACPI shutdown device address +// +#define CLOUDHV_ACPI_SHUTDOWN_IO_ADDRESS 0x03c0 + +// +// 32-bit MMIO memory hole base address +// +#define CLOUDHV_MMIO_HOLE_ADDRESS 0xc0000000 + +// +// 32-bit MMIO memory hole size +// +#define CLOUDHV_MMIO_HOLE_SIZE 0x38000000 + +#endif // __CLOUDHV_H__ diff --git a/OvmfPkg/Include/OvmfPlatforms.h b/OvmfPkg/Include/OvmfPlatform= s.h index 3b85593b70..ad0b0d2803 100644 --- a/OvmfPkg/Include/OvmfPlatforms.h +++ b/OvmfPkg/Include/OvmfPlatforms.h @@ -16,6 +16,7 @@ #include #include #include +#include = // // OVMF Host Bridge DID Address diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c b/OvmfPkg/Libr= ary/AcpiTimerLib/BaseAcpiTimerLib.c index 7c593e8be1..e182ac2b7d 100644 --- a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c @@ -55,6 +55,9 @@ AcpiTimerLibConstructor ( AcpiCtlReg =3D POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL); AcpiEnBit =3D ICH9_ACPI_CNTL_ACPI_EN; break; + case CLOUDHV_DEVICE_ID: + mAcpiTimerIoAddr =3D CLOUDHV_ACPI_TIMER_IO_ADDRESS; + return RETURN_SUCCESS; default: DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n", __FUNCTION__, HostBridgeDevId)); diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c b/OvmfPkg/L= ibrary/AcpiTimerLib/BaseRomAcpiTimerLib.c index 52f3ea2dbf..a223153b2b 100644 --- a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c @@ -53,6 +53,8 @@ AcpiTimerLibConstructor ( AcpiCtlReg =3D POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL); AcpiEnBit =3D ICH9_ACPI_CNTL_ACPI_EN; break; + case CLOUDHV_DEVICE_ID: + return RETURN_SUCCESS; default: DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n", __FUNCTION__, HostBridgeDevId)); @@ -107,6 +109,8 @@ InternalAcpiGetTimerTick ( case INTEL_Q35_MCH_DEVICE_ID: Pmba =3D POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE); break; + case CLOUDHV_DEVICE_ID: + return IoRead32 (CLOUDHV_ACPI_TIMER_IO_ADDRESS); default: DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n", __FUNCTION__, HostBridgeDevId)); diff --git a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c b/OvmfPkg/Libra= ry/AcpiTimerLib/DxeAcpiTimerLib.c index 09076c0ade..3c9efb926f 100644 --- a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c @@ -50,6 +50,9 @@ AcpiTimerLibConstructor ( case INTEL_Q35_MCH_DEVICE_ID: Pmba =3D POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE); break; + case CLOUDHV_DEVICE_ID: + mAcpiTimerIoAddr =3D CLOUDHV_ACPI_TIMER_IO_ADDRESS; + return RETURN_SUCCESS; default: DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n", __FUNCTION__, HostBridgeDevId)); diff --git a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c b/OvmfPkg= /Library/PlatformBootManagerLib/BdsPlatform.c index 186401296a..50bfb45351 100644 --- a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c +++ b/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c @@ -1282,6 +1282,7 @@ PciAcpiInitialization ( PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x6b), PciHostIrqs[3]); // H break; case MICROVM_PSEUDO_DEVICE_ID: + case CLOUDHV_DEVICE_ID: return; default: if (XenDetected ()) { diff --git a/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c b/OvmfPkg/L= ibrary/ResetSystemLib/BaseResetShutdown.c index 21c80e4323..ba92299a3c 100644 --- a/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c +++ b/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c @@ -40,6 +40,9 @@ ResetShutdown ( case INTEL_Q35_MCH_DEVICE_ID: AcpiPmBaseAddress =3D ICH9_PMBASE_VALUE; break; + case CLOUDHV_DEVICE_ID: + IoWrite8 (CLOUDHV_ACPI_SHUTDOWN_IO_ADDRESS, 5 << 2 | 1 << 5); + CpuDeadLoop (); default: ASSERT (FALSE); CpuDeadLoop (); diff --git a/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c b/OvmfPkg/Li= brary/ResetSystemLib/DxeResetShutdown.c index 5a75c32df3..a1c59ad042 100644 --- a/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c +++ b/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c @@ -34,6 +34,9 @@ DxeResetInit ( case INTEL_Q35_MCH_DEVICE_ID: mAcpiPmBaseAddress =3D ICH9_PMBASE_VALUE; break; + case CLOUDHV_DEVICE_ID: + mAcpiPmBaseAddress =3D 0; + break; default: ASSERT (FALSE); CpuDeadLoop (); @@ -56,7 +59,11 @@ ResetShutdown ( VOID ) { - IoBitFieldWrite16 (mAcpiPmBaseAddress + 4, 10, 13, 0); - IoOr16 (mAcpiPmBaseAddress + 4, BIT13); + if (mAcpiPmBaseAddress =3D=3D 0) { + IoWrite8 (CLOUDHV_ACPI_SHUTDOWN_IO_ADDRESS, 5 << 2 | 1 << 5); + } else { + IoBitFieldWrite16 (mAcpiPmBaseAddress + 4, 10, 13, 0); + IoOr16 (mAcpiPmBaseAddress + 4, BIT13); + } CpuDeadLoop (); } diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index d736b85e0d..a534d7845d 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -16,6 +16,7 @@ Module Name: #include #include #include +#include #include #include = @@ -135,21 +136,24 @@ QemuUc32BaseInitialization ( UINT32 LowerMemorySize; UINT32 Uc32Size; = - if (mHostBridgeDevId =3D=3D 0xffff /* microvm */) { - return; - } - - if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - // - // On q35, the 32-bit area that we'll mark as UC, through variable MTR= Rs, - // starts at PcdPciExpressBaseAddress. The platform DSC is responsible= for - // setting PcdPciExpressBaseAddress such that describing the - // [PcdPciExpressBaseAddress, 4GB) range require a very small number of - // variable MTRRs (preferably 1 or 2). - // - ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <=3D MAX_UINT32); - mQemuUc32Base =3D (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress); - return; + switch (mHostBridgeDevId) { + case INTEL_Q35_MCH_DEVICE_ID: + // + // On q35, the 32-bit area that we'll mark as UC, through variable M= TRRs, + // starts at PcdPciExpressBaseAddress. The platform DSC is responsib= le for + // setting PcdPciExpressBaseAddress such that describing the + // [PcdPciExpressBaseAddress, 4GB) range require a very small number= of + // variable MTRRs (preferably 1 or 2). + // + ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <=3D MAX_UINT32); + mQemuUc32Base =3D (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress); + return; + case 0xffff: /* microvm */ + return; + case CLOUDHV_DEVICE_ID: + Uc32Size =3D CLOUDHV_MMIO_HOLE_SIZE; + mQemuUc32Base =3D CLOUDHV_MMIO_HOLE_ADDRESS; + return; } = ASSERT (mHostBridgeDevId =3D=3D INTEL_82441_DEVICE_ID); @@ -778,21 +782,22 @@ QemuInitializeRam ( if (IsMtrrSupported ()) { MtrrGetAllMtrrs (&MtrrSettings); = - // - // MTRRs disabled, fixed MTRRs disabled, default type is uncached - // - ASSERT ((MtrrSettings.MtrrDefType & BIT11) =3D=3D 0); - ASSERT ((MtrrSettings.MtrrDefType & BIT10) =3D=3D 0); - ASSERT ((MtrrSettings.MtrrDefType & 0xFF) =3D=3D 0); - - // - // flip default type to writeback - // - SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06); - ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables); - MtrrSettings.MtrrDefType |=3D BIT11 | BIT10 | 6; - MtrrSetAllMtrrs (&MtrrSettings); + if (mHostBridgeDevId !=3D CLOUDHV_DEVICE_ID) { + // + // MTRRs disabled, fixed MTRRs disabled, default type is uncached + // + ASSERT ((MtrrSettings.MtrrDefType & BIT11) =3D=3D 0); + ASSERT ((MtrrSettings.MtrrDefType & BIT10) =3D=3D 0); + ASSERT ((MtrrSettings.MtrrDefType & 0xFF) =3D=3D 0); = + // + // flip default type to writeback + // + SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06); + ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables); + MtrrSettings.MtrrDefType |=3D BIT11 | BIT10 | 6; + MtrrSetAllMtrrs (&MtrrSettings); + } // // Set memory range from 640KB to 1MB to uncacheable // diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index df2d9ad015..cad6a49680 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -346,6 +346,9 @@ MiscInitialization ( // BuildCpuHob (mPhysMemAddressWidth, 16); = + PcdStatus =3D PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId); + ASSERT_RETURN_ERROR (PcdStatus); + // // Determine platform type and save Host Bridge DID to PCD // @@ -372,14 +375,18 @@ MiscInitialization ( MICROVM_PSEUDO_DEVICE_ID); ASSERT_RETURN_ERROR (PcdStatus); return; + case CLOUDHV_DEVICE_ID: + DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor host bridge\n", __FUNCTION= __)); + PcdStatus =3D PcdSet16S (PcdOvmfHostBridgePciDevId, + CLOUDHV_DEVICE_ID); + ASSERT_RETURN_ERROR (PcdStatus); + return; default: DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n", __FUNCTION__, mHostBridgeDevId)); ASSERT (FALSE); return; } - PcdStatus =3D PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId); - ASSERT_RETURN_ERROR (PcdStatus); = // // If the appropriate IOspace enable bit is set, assume the ACPI PMBA has -- = 2.30.2 --------------------------------------------------------------------- Intel Corporation SAS (French simplified joint stock company) Registered headquarters: "Les Montalets"- 2, rue de Paris, = 92196 Meudon Cedex, France Registration Number: 302 456 199 R.C.S. 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