From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) by mx.groups.io with SMTP id smtpd.web11.4273.1622176972339693225 for ; Thu, 27 May 2021 21:42:52 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmx.net header.s=badeba3b8450 header.b=NDaarkCV; spf=pass (domain: gmx.de, ip: 212.227.17.20, mailfrom: xypron.glpk@gmx.de) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1622176966; bh=rKt701hux/jEUOWIcVeYuBnzl3NreSfXIbAjVp8JAKo=; h=X-UI-Sender-Class:Date:In-Reply-To:References:Subject:To:CC:From; b=NDaarkCVotSNB74NDq59wm+3HRe+PqAhys/HXBTGyBerLAjcxOJKHlO0camgqg0Wh ubb2DVh7Q6RL/6sMuVNqd4wBCfkknUA4aiOxxllSM9lXbf96Q+XkoE2vho4tZtbplJ HnsVxJYe3tC5SFJUcRrUtAiuypKiIi74mzRbX+tE= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from android-37777258dcaea06b.fritz.box ([62.143.247.63]) by mail.gmx.net (mrgmx105 [212.227.17.168]) with ESMTPSA (Nemesis) id 1Mz9Ux-1lRMur0ojb-00wG2T; Fri, 28 May 2021 06:42:46 +0200 Date: Fri, 28 May 2021 06:42:44 +0200 User-Agent: K-9 Mail for Android In-Reply-To: <20210527144113.206426-1-sunilvl@ventanamicro.com> References: <20210527144113.206426-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Subject: Re: [PATCH] Add support for RISCV GOT/PLT relocations To: Sunil V L ,devel@edk2.groups.io CC: sunil.vl@gmail.com,Abner Chang ,Daniel Schaefer From: "Heinrich Schuchardt" Message-ID: <6A934026-DA4B-4151-BBE0-34D80B255880@gmx.de> X-Provags-ID: V03:K1:6CX72blP8aIiSVTxI5uWzq1fZvdAhYt6fNTYIVuJZCPpWOJO964 dgWGTeaPMruaqR2fF7bmEIxUQsrlpJQAIS0nHQWZpk9+uVEd4mHVVUVvasJc868VjCe8SUJ P+7J6vXyg0a4Gxg6CoiqcnI90rIfgLkRGXfjd2U4B3c4BeT+SJv/HzobaRVPcsdBVz0TFtd CmwpJPlxydyo6Ykto53Zg== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1;V03:K0:BgVaTAsJMTo=:7AQGf44Ka6rnIWaPtPOVxF hZu0r/h4CBqa5MOeI1qwbp3BbXFCDvIT/SbRLbU0hvZiopNogtM21TObKv/K6yhL5dt5ESW3/ Y9ynQx0DZ79/U+RQZJMAW2M9I8iO0gAgya5Ma2AG+P/j+ub5yGYev4MtydTPwbc4bmhUQpTgU CGgZUmrBV/WDJIpQ82cmcfav7hMj+q55v6q/sM++3CZhwbaOeD9X2DaMR4CUyoKv+8BOMcn3a 7hdS2TeWo7JwcdY0MTcgU2351r2NUXaOFgBwdZCPGTP0RTIJ2u7Qiq3MbkiDJ+V3yTg+Ur/rF 8mlmjRZbf3MtQRibN3+s+uvgtaZevv+xL2TtfB/gGM/m/P72er2Ttt4jpgSFiIsQGBmgOl3F9 bzNSW+GjwuRjfQHc1qQogw+FtuvBCbMYpJWaAELC2t2n1sUopXGzlOMqTu8m5zQgeWntRm3m+ 2ciEtAkuj36yjuJPpwGU1he3oJhI1VddxLMzP4ufxAxt5q5jq/SUWzjvlHYc0V78PjcdDsfrA wMHG9shjAjxZOIEzhVy/7RtY/C+XQDTTKglTKpQ6EWErygsi6rHFRMpi34qEWT6pT3iMYiL82 FA1ryxsPseTZz8CMhQFWXIYu0a2tDQRLwJVXnXpMAXw64HnshvrBASBwTWeTwZyPFjXwIJJLM CYB8HqeiVENdfZfSxiiTzuUmH1jBpch9kuGWT5DhCwXZ5QT/AlkECNorpYRtY7Gtth+XfTFlz 7P/9p66QSqOTtnu+lfwT6YEUFM8IYMsL0KEM+9ppEANqVSID+qGzPGFBwrgrSZQWvuLTBmF9n 8wRfNuqEkN2gqDyExAaTb3Z56PAHRpm6T1Vh0ZMrYE49oykkLzNo+bx43IvT1ENvA/xD0u9pT P7PIwK0wNwEVI4S+53DsmjqcfT8xr/Wh+pEBba/cbJEACOCP0PN0E2KakiAqi7uThYxXeod6P RE/QlpSDSW1MG1nRg6H1IMCCLwVrPpDmLHfaruMGQFcWRW7ohhU8GZGfmac2pgqjLRAuiiIh1 rP6w6zAD6RekKDBGqLnbMvwfziWJRfLmunbAyrNOz2XrE+Rw2JB+JEykVdXb27iTBae7PeBtI UUqMEsR/Brw474YZJfNpLLnXYSPmn2GtojG Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Am 27=2E Mai 2021 16:41:13 MESZ schrieb Sunil V L : >Ref: https://bugzilla=2Etianocore=2Eorg/show_bug=2Ecgi?id=3D3096 > >This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20 >relocations=2E > gnu-efi tries to avoid GOT based relocations on ARM using #if defined(__GNUC__) && !__STDC_HOSTED__ #pragma GCC visibility push (hidden) #endif Maybe this is something we should additionally explore=2E Best regards Heinrich >Signed-off-by: Sunil V L >Cc: Abner Chang >Cc: Daniel Schaefer >Cc: Heinrich Schuchardt >--- > BaseTools/Source/C/GenFw/Elf64Convert=2Ec | 45 +++++++++++++++++++++---- > 1 file changed, 39 insertions(+), 6 deletions(-) > >diff --git a/BaseTools/Source/C/GenFw/Elf64Convert=2Ec >b/BaseTools/Source/C/GenFw/Elf64Convert=2Ec >index d097db8632=2E=2Ed05dcf9992 100644 >--- a/BaseTools/Source/C/GenFw/Elf64Convert=2Ec >+++ b/BaseTools/Source/C/GenFw/Elf64Convert=2Ec >@@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset; > STATIC UINT8 *mRiscVPass1Targ =3D NULL;> > STATIC Elf_Shdr *mRiscVPass1Sym =3D NULL;> > STATIC Elf64_Half mRiscVPass1SymSecIndex =3D 0;> >+STATIC INT32 mRiscVPass1Offset;> >+STATIC INT32 mRiscVPass1GotFixup;> > > > //> > // Initialization Function> >@@ -479,11 +481,11 @@ WriteSectionRiscV64 ( > break;> > > > case R_RISCV_32:> >- *(UINT32 *)Targ =3D (UINT32)((UINT64)(*(UINT32 *)Targ) - >SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]);> >+ *(UINT64 *)Targ =3D Sym->st_value + Rel->r_addend;> > break;> > > > case R_RISCV_64:> >- *(UINT64 *)Targ =3D *(UINT64 *)Targ - SymShdr->sh_addr + >mCoffSectionsOffset[Sym->st_shndx];> >+ *(UINT64 *)Targ =3D Sym->st_value + Rel->r_addend;> > break;> > > > case R_RISCV_HI20:> >@@ -533,6 +535,18 @@ WriteSectionRiscV64 ( > mRiscVPass1SymSecIndex =3D 0;> > break;> > > >+ case R_RISCV_GOT_HI20:> >+ Value =3D (Sym->st_value - Rel->r_offset);> >+ mRiscVPass1Offset =3D RV_X(Value, 0, 12);> >+ Value =3D RV_X(Value, 12, 20);> >+ *(UINT32 *)Targ =3D (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12));> >+> >+ mRiscVPass1Targ =3D Targ;> >+ mRiscVPass1Sym =3D SymShdr;> >+ mRiscVPass1SymSecIndex =3D Sym->st_shndx;> >+ mRiscVPass1GotFixup =3D 1;> >+ break;> >+> > case R_RISCV_PCREL_HI20:> > mRiscVPass1Targ =3D Targ;> > mRiscVPass1Sym =3D SymShdr;> >@@ -545,11 +559,17 @@ WriteSectionRiscV64 ( >if (mRiscVPass1Targ !=3D NULL && mRiscVPass1Sym !=3D NULL && >mRiscVPass1SymSecIndex !=3D 0) {> > int i;> > Value2 =3D (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));> >- Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));> >- if(Value & (RISCV_IMM_REACH/2)) {> >- Value |=3D ~(RISCV_IMM_REACH-1);> >+> >+ if(mRiscVPass1GotFixup) {> >+ Value =3D (UINT32)(mRiscVPass1Offset);> >+ } else {> >+ Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));> >+ if(Value & (RISCV_IMM_REACH/2)) {> >+ Value |=3D ~(RISCV_IMM_REACH-1);> >+ }> > }> >Value =3D Value - (UINT32)mRiscVPass1Sym->sh_addr + >mCoffSectionsOffset[mRiscVPass1SymSecIndex];> >+> > if(-2048 > (INT32)Value) {> > i =3D (((INT32)Value * -1) / 4096);> > Value2 -=3D i;> >@@ -569,12 +589,22 @@ WriteSectionRiscV64 ( > }> > }> > > >- *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | >(RV_X(*(UINT32*)Targ, 0, 20));> >+ if(mRiscVPass1GotFixup) {> >+ *(UINT32 *)Targ =3D (RV_X((UINT32)Value, 0, 12) << 20)> >+ | (RV_X(*(UINT32*)Targ, 0, 20));> >+ /* Convert LD instruction to ADDI */> >+ *(UINT32 *)Targ =3D ((*(UINT32 *)Targ & ~0x707f) | 0x13);> >+ }> >+ else {> >+ *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | >(RV_X(*(UINT32*)Targ, 0, 20));> >+ }> >*(UINT32 *)mRiscVPass1Targ =3D (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 >*)mRiscVPass1Targ, 0, 12));> > }> > mRiscVPass1Sym =3D NULL;> > mRiscVPass1Targ =3D NULL;> > mRiscVPass1SymSecIndex =3D 0;> >+ mRiscVPass1Offset =3D 0;> >+ mRiscVPass1GotFixup =3D 0;> > break;> > > > case R_RISCV_ADD64:> >@@ -586,6 +616,7 @@ WriteSectionRiscV64 ( > case R_RISCV_GPREL_I:> > case R_RISCV_GPREL_S:> > case R_RISCV_CALL:> >+ case R_RISCV_CALL_PLT:> > case R_RISCV_RVC_BRANCH:> > case R_RISCV_RVC_JUMP:> > case R_RISCV_RELAX:> >@@ -1528,6 +1559,7 @@ WriteRelocations64 ( > case R_RISCV_GPREL_I:> > case R_RISCV_GPREL_S:> > case R_RISCV_CALL:> >+ case R_RISCV_CALL_PLT:> > case R_RISCV_RVC_BRANCH:> > case R_RISCV_RVC_JUMP:> > case R_RISCV_RELAX:> >@@ -1537,6 +1569,7 @@ WriteRelocations64 ( > case R_RISCV_SET16:> > case R_RISCV_SET32:> > case R_RISCV_PCREL_HI20:> >+ case R_RISCV_GOT_HI20:> > case R_RISCV_PCREL_LO12_I:> > break;> > >