From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.34464.1591634700690710792 for ; Mon, 08 Jun 2020 09:45:00 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: ard.biesheuvel@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 555401FB; Mon, 8 Jun 2020 09:45:00 -0700 (PDT) Received: from [192.168.1.69] (unknown [10.37.8.184]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 44B963F73D; Mon, 8 Jun 2020 09:44:57 -0700 (PDT) Subject: Re: [edk2-devel] [PATCH] ArmPlatformPkg/PL011UartLib: Add PCD for FIFO depth To: ipark@nvidia.com, devel@edk2.groups.io References: <1266.1591627626574447386@groups.io> From: "Ard Biesheuvel" Message-ID: <6a925a5e-4de0-99dd-7dce-00cc00628315@arm.com> Date: Mon, 8 Jun 2020 18:44:51 +0200 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:68.0) Gecko/20100101 Thunderbird/68.8.1 MIME-Version: 1.0 In-Reply-To: <1266.1591627626574447386@groups.io> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit On 6/8/20 4:47 PM, Irene Park via Groups.Io wrote: > Hi Ard, > I feel bad that I confused you. I'll update the commit message later. > SBSA spec doesn't "mandate" that the optional registers such as PID2 are > present in a UART compliant to PL011. > Therefore this register access to PID2 will generate a fault onto SOC > when its UART doesn't provide such registers. > PID2 is used to determine the FIFO depth in the library so I'd like to > propose a new PCD to define a FIFO depth. I'd prefer it if we could change the existing code so that the register is never checked if gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth is set to a value > 0