From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by mx.groups.io with SMTP id smtpd.web08.4375.1664231993282755353 for ; Mon, 26 Sep 2022 15:39:53 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=qbyxn/Cu; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: quicinc.com, ip: 199.106.114.38, mailfrom: quic_llindhol@quicinc.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1664231993; x=1695767993; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=YEJqQgLZ5jiK9ZgaFL0mwUv+Ms9z+lEFlP3dDCDGX3Y=; b=qbyxn/Cu7y63uqktOKSJ2bAJZD0qtjEWYD+ttBXSrBMGA1+LYK5dk802 UsfX2RF3URx17byYO3I6bMAUp338JfFU16qY2hBoO92iR3d0KpmdNX89q cHMdJ58sTxZ4970yaN17Ex5v9LKiI957zbGnhIG9v5e+OrAg+ytbY9hU8 c=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-01.qualcomm.com with ESMTP; 26 Sep 2022 15:39:53 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.45.79.139]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2022 15:39:52 -0700 Received: from [10.110.26.2] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 26 Sep 2022 15:39:52 -0700 Message-ID: <6c0a80ce-1888-f6bf-51d3-c9c1e94973a9@quicinc.com> Date: Mon, 26 Sep 2022 15:39:51 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 Subject: Re: [edk2-devel] [PATCH v3 09/16] ArmPlatformPkg/PrePeiCore: permit entry with the MMU enabled To: , CC: Alexander Graf References: <20220926082511.2110797-1-ardb@kernel.org> <20220926082511.2110797-10-ardb@kernel.org> From: "Leif Lindholm" In-Reply-To: <20220926082511.2110797-10-ardb@kernel.org> Return-Path: quic_llindhol@quicinc.com X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit On 2022-09-26 01:25, Ard Biesheuvel wrote: > Some platforms may set up a preliminary ID map in flash and enter EFI > with the MMU and caches enabled, as this removes a lot of the complexity > around cache coherency. Let's take this into account, and avoid touching > the MMU controls or perform cache invalidation when the MMU is enabled > at entry. > > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm / Leif > --- > ArmPlatformPkg/PrePeiCore/PrePeiCore.c | 22 +++++++++++--------- > 1 file changed, 12 insertions(+), 10 deletions(-) > > diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c > index 9c4b25df953d..8b86c6e69abd 100644 > --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c > +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c > @@ -58,17 +58,19 @@ CEntryPoint ( > IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint > > ) > > { > > - // Data Cache enabled on Primary core when MMU is enabled. > > - ArmDisableDataCache (); > > - // Invalidate instruction cache > > - ArmInvalidateInstructionCache (); > > - // Enable Instruction Caches on all cores. > > - ArmEnableInstructionCache (); > > + if (!ArmMmuEnabled ()) { > > + // Data Cache enabled on Primary core when MMU is enabled. > > + ArmDisableDataCache (); > > + // Invalidate instruction cache > > + ArmInvalidateInstructionCache (); > > + // Enable Instruction Caches on all cores. > > + ArmEnableInstructionCache (); > > > > - InvalidateDataCacheRange ( > > - (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase), > > - PcdGet32 (PcdCPUCorePrimaryStackSize) > > - ); > > + InvalidateDataCacheRange ( > > + (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase), > > + PcdGet32 (PcdCPUCorePrimaryStackSize) > > + ); > > + } > > > > // > > // Note: Doesn't have to Enable CPU interface in non-secure world, >